Hardware Emulation Node Coordination in Distributed Simulation
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Solution Overview
Problem
Distributed simulation systems for complex electronic systems face limitations due to the varying processing requirements across nodes, leading to reduced simulation throughput, as the overall system is bottlenecked by the slowest node, and existing methods struggle with coordinating and synchronizing simulations effectively across multiple nodes.
Innovation Solution
A distributed design verification system that includes simulation nodes and hardware emulation nodes, with field programmable gate array (FPGA) devices for hardware emulation, allowing for coordinated distributed design verification through the exchange of simulation information and using a distributed control node to coordinate simulations and emulations, along with a hub for message routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If distributed simulation is used to handle large electronic systems, then simulation capability is improved, but coordination and synchronization complexity increases
Solution Approach 1:
A central controller is introduced as an intermediary component to manage coordination and synchronization between distributed simulation nodes. The controller receives simulation data from multiple nodes, processes it centrally, and distributes updated information back to nodes, thereby simplifying the complex coordination tasks that would otherwise require direct peer-to-peer management between all nodes.
Solution Approach 2:
The simulation system is segmented into independent nodes that can operate autonomously while communicating through standardized interfaces. Each node handles a specific portion of the electronic system model, and the segmentation allows for modular coordination where the central controller manages overall synchronization without requiring complex direct coordination between every node pair.
2Productivity
If hardware emulation nodes are added to the distributed simulation system, then simulation throughput is improved, but system cost increases
Solution Approach 1:
Hardware emulation nodes are designed with universal functionality that allows them to serve multiple purposes: they can simulate portions of electronic systems, provide hardware acceleration for critical sections, and act as coordination points in the distributed architecture. This multi-functionality justifies the added cost by delivering multiple performance benefits from a single infrastructure investment.
Solution Approach 2:
The system allows dynamic adjustment of the number and configuration of hardware emulation nodes based on simulation requirements. Nodes can be added or removed from the distributed simulation environment depending on the complexity of the electronic system being simulated, enabling cost-effective resource allocation where hardware emulation is applied only when and where it provides the most benefit.
3Manufacturing precision
If all nodes must complete processing for a particular simulated time interval before proceeding, then simulation accuracy is improved, but simulation throughput is reduced
Solution Approach 1:
The central controller implements a feedback mechanism that monitors completion status of all simulation nodes and coordinates the progression of simulation time intervals. Nodes that complete their processing early receive feedback signals and can prepare for the next interval or perform validation tasks, while the controller ensures that all nodes are synchronized at critical decision points, maintaining accuracy without requiring all nodes to wait idly for the slowest node.
Data Source
AI summary
A system for interfacing hardware emulation to software simulation environments may include a simulation node configured to simulate a first portion of a system under test and a hardware emulation node configured to emulate a second portion of the system under test. The hardware emulation node may also be configured to exchange simulation information (such as representations of signal values obtained as output from the emulated portion of the system under test) with the simulation node. The hardware emulation node may contain a field programmable gate array devices (FPGA) configured to perform the hardware emulation. The FPGA may be mounted on an expansion board, such as a PCI (Peripheral Component Interconnect) board.