Hardware Monitors for Exhaustive Memory Unit Verification
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Solution Overview
Problem
Existing memory unit verification systems face challenges in designing a generic method to verify the operation of memory units due to their varied features such as multiple access ports, partial reads/writes, clock gating, and pipelining, making it difficult to exhaustively verify their behavior.
Innovation Solution
The implementation of hardware monitors with detection logic to monitor control and data signals for symbolic writes and reads, and assertion verification logic to ensure that read data matches write data, allowing formal verification tools to exhaustively verify the operation of memory units across different configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a generic verification system is designed to handle diverse memory unit features, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal verification framework that can handle multiple memory unit configurations (single-port, multi-port, pipelined, non-pipelined, clock-gated, unclocked) through a single generic hardware monitor design. The monitor uses configurable detection logic that can be adapted to different memory types without requiring separate verification systems for each configuration, thereby achieving multi-functionality while maintaining simplicity.
Solution Approach 2:
The verification system utilizes parameterizable detection logic that can be configured through control signals to match different memory unit characteristics. By changing verification parameters (such as port configuration, pipelining status, and clock gating enablement) rather than changing the fundamental monitor architecture, the system achieves adaptability across diverse memory types without increasing structural complexity.
2Measurement precision
If exhaustive verification is performed on memory units with multiple features, then measurement precision is improved, but time consumption increases
Solution Approach 1:
The verification process is segmented into discrete verification cycles, each handling a specific memory operation (read or write). The hardware monitor divides the complex verification task into manageable segments by tracking individual control signals (read_en, write_en, clock_gating_en) and verifying operations independently. This segmentation enables exhaustive verification while reducing time consumption through parallelizable cycle-based verification.
Solution Approach 2:
The system implements feedback mechanisms where the hardware monitor continuously tracks the state of memory operations and compares read data against previously written data. The verification logic uses feedback from detection logic to determine when verification cycles should terminate or continue, enabling efficient exhaustive verification by stopping unnecessary verification cycles once all possible operations are confirmed.
3Reliability
If hardware monitors are designed to detect all symbolic reads and writes, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent extracts only the essential verification functionality from complex memory operations. The hardware monitor focuses solely on detecting symbolic reads and writes by monitoring specific control signals, rather than attempting to verify every possible memory operation detail. This extraction approach maintains high reliability for the critical verification function while keeping the monitor design simple and manageable.
Solution Approach 2:
The verification system is self-sufficient, with the hardware monitor autonomously detecting and verifying memory operations without requiring external intervention. The detection logic automatically identifies symbolic reads and writes by monitoring control signals, and the assertion verification logic independently compares read data against write data. This self-service capability ensures reliable verification while avoiding the complexity of external verification systems.
Data Source
AI summary
Hardware monitors which can be used by a formal verification tool to exhaustively verify a hardware design for a memory unit. The hardware monitors include detection logic to monitor one or more control signals and/or data signals of an instantiation of the memory unit to detect symbolic writes and symbolic reads. In some examples a symbolic write is a write of symbolic data to a symbolic address; and in other examples a symbolic write is a write of any data to a symbolic address. A symbolic read is a read of the symbolic address. The hardware monitors also include assertion verification logic that verifies an assertion that read data corresponding to a symbolic reads matches write data associated with one or more symbolic writes preceding the read.