Hardware Queue Manager for Lock-Free Multi-Core Queue Access
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Solution Overview
Problem
Managing queue data structures in digital systems is costly for software, requiring many instructions and excessive time, which reduces bandwidth for other tasks, especially in systems with multiple processor cores.
Innovation Solution
A hardware-based queue manager that supports multiple processor cores, allowing efficient management of queue data structures by supporting various element sizes, quantities, and ordered lists, providing lock-free access and virtualization to prevent contention among processor cores.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If software manages queue data structures in digital systems, then queue management tasks can be performed, but it requires many instructions and excessive time, reducing bandwidth for other tasks
Solution Approach 1:
The patent replaces software-based queue management with a hardware queue manager that uses dedicated circuitry, registers, and state machines to perform queue operations. This mechanical/electronic substitution eliminates the need for software instructions to manage queues, dramatically reducing execution time and freeing up processor bandwidth while maintaining full queue management functionality.
2Productivity
If a hardware queue manager supports multiple processor cores, then access efficiency improves, but contention among cores may occur without proper virtualization
Solution Approach 1:
The hardware queue manager implements virtualization by dividing the queue management resources into multiple virtual instances, each accessible by a specific processor core. This segmentation allows each core to have dedicated access paths and state machines, eliminating contention while maintaining efficient hardware-based queue operations across multiple cores simultaneously.
3Productivity
If lock-free access is implemented in the hardware queue manager, then performance improves, but complexity of ensuring data consistency increases
Solution Approach 1:
The hardware queue manager uses self-service mechanisms where dedicated state machines and registered interfaces automatically handle data consistency and synchronization for each processor core. The virtualized architecture provides inherent isolation between cores, eliminating the need for complex locking protocols while maintaining data integrity through hardware-enforced access rules and dedicated resource allocation.
Data Source
AI summary
A hardware-based queue manager is implemented in a network accelerator. The queue manager may receive input from a processor core into a set of registers designated for that processor core. Other sets of registers may be designated for other processor cores. The queue manager reads the input in the set of registers, which triggers the queue manager to begin a transaction, such as reading or writing to a queue data structure in a data memory. The queue data structure may handle multiple sizes of queue data structures.