Transaction Processing TRIZ Cases
- Sequencer-Coordinated State Machines for ACID Transaction Processing
Atomic message ordering, local queues, and service state machines enable ACID distributed transactions with less coordination overhead than 2PC or Saga.
- Hardware Queue Manager for Lock-Free Multi-Core Queue Access
A hardware queue manager enables lock-free multi-core queue access.
- Disaggregated Memory Access via InfiniBand Transaction Datapaths
A software-defined datapath reformats interconnect transactions for remote memory, improving utilization with managed latency.
- Enlisting Single Phase Commit Resources in Two Phase Transactions
Recording a unique identifier stabilizes single phase commit decisions before two phase voting, preventing atomicity violations.
- HTM-Assisted Combining Framework for Concurrent Data Structures
Hardware transactional memory assists flat combining to synchronize concurrent data structure access.
- Synchronous Transaction Framework State Persistence
A synchronous transaction framework captures and persists intermediate states within dedicated objects to enable precise control over execution flow.
- SPI Emulation Switch for One-to-Many Data Transfer
An emulation switch interfaces SPI masters with multiple clients to enable high-speed one-to-many communication.
- Transactional Memory Support for CXL Devices
CXL devices implement transactional memory operations using speculative execution and conflict detection circuitry.
- Dynamic Bus Arbitration for Multi-Peripheral QoS Prioritization
Ranking transactions by rank prevents high-priority delays and improves reliability.
- Message Protocol for PCIe Data Processing Systems
A message protocol divides large write bursts into ordered sequences of smaller requests for efficient interconnect transmission.
- Transactional Memory Automaton Engine for Packet Traffic Analysis
A transactional memory system with local byte-wise compare and NFA resources processes incoming byte streams without intermediate read operations.
- Data Bus Bridge for Width Conversion and Burst Breaking
A data bus bridge splits wide transactions into narrower bursts to adapt between domains.
- Epoch-Based Transaction Resource Reservation for Forward Progress
A responder reserves transaction resources across discrete epochs to prioritize retransmitted requests from previous time windows.
- Transactional Memory Grouping for Performance Optimization
Transaction grouping segments concurrent programs to resolve performance compromises from generic synchronization.
- Transactional Memory Lock Translation for Concurrency Bottlenecks
Binary translation replaces lock instructions with transactional acquire and release operations, reducing memory contention without programmer intervention.
- Non-repudiable Transaction Protocol via Trusted Third Party
A transaction manager issues non-repudiation tokens to verify work origins and receipts, preventing parties from falsely repudiating distributed transactions.
- Coupling Facility Asynchronous Duplexing for Sysplex Latency
Sequence values in command blocks enable asynchronous loading to reduce system latency while preserving data consistency.
- SoC Memory Controller Interconnect Transaction Routing
Central processing circuitry routes interconnect transactions to specific memory controllers, reducing slave connector count and design complexity.
- Transaction Availability Indicator for Processing Overload
A transaction availability indicator filters incoming requests before execution.
- Map Reduce Scheduler Service for Spark Job Orchestration
A Map/Reduce scheduler service abstracts distributed cluster management complexity for developers via a centralized HTTP API.
- On-Chip Interconnect Burst Read Chunking
Reconstructing chunk identifiers in the interconnect eliminates buffering requirements, reducing latency and power consumption during burst read operations.
- Synchronizer Circuit for Video Codec Memory Latency
Hardware synchronization reduces encoding latency from 20 ms to 3 ms by eliminating interrupt handling overhead.
- Hybrid Memory Controller Soft Hard Logic Segmentation
Segmenting a memory controller into soft and hard logic reduces resource overhead while maintaining customization for specific applications.