SoC Memory Controller Interconnect Transaction Routing
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Solution Overview
Problem
The existing system-on-chip (SoC) designs face increased design complexity, size, and manufacturing costs due to the need for additional slave connectors to achieve desired throughput in system memory, which scales poorly with memory size.
Innovation Solution
A memory management system with processing circuitry that identifies and manages multiple memory controllers to facilitate transactions between the interconnect and system memory, reducing the number of slave connectors required by optimizing their distribution based on throughput rather than memory size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of slave connectors is increased to achieve desired throughput, then the throughput is improved, but the design complexity and manufacturing cost increase
Solution Approach 1:
Multiple memory controllers are merged and managed by a single processing circuitry unit that receives transaction requests from the interconnect, identifies the appropriate memory controller, and coordinates transactions. This consolidation reduces the number of slave connectors needed while maintaining throughput performance.
Solution Approach 2:
The processing circuitry acts as an intermediary between the interconnect and multiple memory controllers. It receives transaction requests, identifies the target memory controller based on memory addresses, and manages the transaction flow, thereby reducing the direct connection requirements between the interconnect and memory subsystem.
2Quantity of substance
If the number of slave connectors is increased to support larger memory size, then the memory capacity is improved, but the design complexity and size increase
Solution Approach 1:
The processing circuitry performs multiple functions: it manages multiple memory controllers, identifies appropriate controllers based on memory addresses, coordinates transactions, and maintains ordering. This multi-functional approach allows the system to support larger memory capacities without proportionally increasing the number of slave connectors or overall system complexity.
3Productivity
If additional slave connectors are included in the interconnect, then the throughput is improved, but the manufacturing cost increases
Solution Approach 1:
Multiple memory controller functions are combined under a single processing circuitry unit that manages all transactions centrally. This merging reduces the number of slave connectors required in the interconnect, thereby reducing manufacturing complexity and cost while maintaining the necessary throughput capability.
Data Source
AI summary
A memory management system for facilitating communication between an interconnect and a system memory of a system-on-chip includes a plurality of memory controllers coupled with the system memory, and processing circuitry coupled with the interconnect and the plurality of memory controllers. The processing circuitry is configured to receive a transaction request from the interconnect, and identify a memory controller of the plurality of memory controllers that is associated with the received transaction request. Further, the processing circuitry is configured to provide the transaction request to the identified memory controller for an execution of a transaction associated with the received transaction request. The processing circuitry is further configured to receive a transaction response to the provided transaction request from the memory controller, and provide the received transaction response to the interconnect after a previous transaction response associated with a previous transaction request is provided to the interconnect.