Message Protocol for PCIe Data Processing Systems

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Solution Overview

Problem

The existing message protocols for data processing systems, particularly in systems-on-chip (SoCs), face inefficiencies and performance reductions due to the need to divide large transactions into smaller requests, leading to increased message header overhead and reduced throughput in PCIe peer-to-peer transactions.

Innovation Solution

A high-efficiency message protocol that divides large write bursts into ordered sequences of write requests, combines them at a write combiner node, and preserves the Ordered Write Observation property to ensure early completion of transactions, reducing message overhead and improving bandwidth.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the transaction size of a request is larger than the maximum transaction size supported by the interconnect, then the request must be divided into several smaller requests, but this significantly reduces interconnect efficiency, performance and throughput, and increases message header overhead

Engineering Contradiction:
Improvetransaction size supportVSAvoidinterconnect throughput
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent applies segmentation by dividing a large write burst into multiple smaller write requests that can be transmitted through the interconnect. Each write request is a segment of the original large transaction, allowing the system to handle transactions larger than the interconnect's maximum transaction size while maintaining compatibility with the interconnect's size limitations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent combines multiple write requests at the write combiner into a single write burst that is sent to the slave device. This merging process consolidates the segmented requests back into a larger transaction, reducing the number of message headers needed and improving interconnect efficiency by eliminating redundant header overhead.

Inventive Principle:
Principle #5Merging (Combining)

2Adaptability or versatility

If the transaction size of a request is larger than the maximum transaction size supported by the interconnect, then the request must be divided into several smaller requests, but this increases message header overhead for requesters, completers and slave devices

Engineering Contradiction:
Improvetransaction size supportVSAvoidmessage header overhead
Core Design Contradiction:
Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The patent segments the original large transaction into multiple write requests, each with its own message header. While this creates multiple headers, it enables the system to support transactions larger than the interconnect's maximum size limitation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The write combiner merges multiple write requests into a single write burst, eliminating the need for separate message headers at the slave device for each individual request. This consolidation significantly reduces the total message header overhead that would otherwise be present if each segmented request were processed independently with full headers.

Inventive Principle:
Principle #5Merging (Combining)

3Adaptability or versatility

If large transactions are divided into smaller requests, then the interconnect can handle them, but this reduces interconnect efficiency and performance

Engineering Contradiction:
Improvetransaction size compatibilityVSAvoidinterconnect performance
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent segments large transactions into smaller write requests that fit within the interconnect's maximum transaction size, enabling compatibility with the interconnect's size constraints while maintaining the ability to handle large overall data transfers.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The write combiner merges multiple segmented write requests back into a consolidated write burst before sending to the slave device. This merging improves interconnect performance by reducing the number of separate transaction cycles needed and minimizing the overhead associated with individual request handling, thereby increasing overall throughput and efficiency.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11074206B1Message protocol for a data processing system
Publication Date: 2021.07.27 ARM LTD
  • US11074206B1 patent drawing
  • US11074206B1 patent drawing
  • US11074206B1 patent drawing

AI summary

The present disclosure advantageously provides a method and system for transferring data over at least one interconnect. A request node, coupled to an interconnect, receives a first write burst from a first device over a first connection, divides the first write burst into an ordered sequence of smaller write requests based on the size of the first write burst, and sends the ordered sequence of write requests to a home node coupled to the interconnect. The home node generates an ordered sequence of write transactions based on the ordered sequence of write requests, and sends the ordered sequence of write transactions to a write combiner coupled to the home node. The write combiner combines the ordered sequence of write transactions into a second write burst that is the same size as the first write burst, and sends the second write burst to a second device over a second connection.