Hardware Redirector Hit Rate via Usage History Table
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Solution Overview
Problem
Modern microprocessors face inefficiencies in accessing and executing translated instruction set architecture (ISA) code, where frequently-executed translations are difficult to retrieve, leading to suboptimal processing pipeline performance and increased power consumption.
Innovation Solution
A dynamic binary translator and on-core hardware structure, known as the hardware redirector, efficiently manages the retrieval and execution of translated ISA code by indexing frequently-used translations and using usage information to maintain or evict entries, allowing for execution in a translation mode that bypasses the hardware decoder, thereby improving access times and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If translations are stored in a limited-size hardware redirector structure, then access time to translations is reduced, but frequently-executed translations may be evicted and become difficult to retrieve
Solution Approach 1:
The patent divides the translation storage system into two segments: a hardware redirector structure for fast access and a usage history table for persistent storage. The hardware redirector holds currently active translations for immediate retrieval, while the usage history table maintains evicted translations using least-recently-used (LRU) tracking. This segmentation allows the system to maintain fast access times while preserving frequently-used translations that may be evicted from the hardware structure.
Solution Approach 2:
The system performs preliminary actions by tracking usage information and maintaining an LRU history before translations are actually needed again. When a translation is evicted from the hardware redirector, its usage history is preserved in the usage history table, allowing the system to quickly restore it if needed without requiring a full re-generation or lengthy search process.
2Device complexity
If the hardware redirector maintains fewer entries to reduce complexity, then device complexity is reduced, but the hit rate decreases and more translations are difficult to access
Solution Approach 1:
The usage history table acts as an intermediary between the hardware redirector and the translation storage. It records the LRU information of evicted translations and enables the system to quickly determine whether a missed translation should be restored to the hardware redirector. This intermediary structure allows the hardware redirector to maintain a smaller size while the system as a whole achieves high productivity through efficient translation access.
3Reliability
If the system uses a larger hardware redirector to increase hit rate, then more translations are readily accessible, but the area occupied by the hardware structure increases
Solution Approach 1:
The patent segments the translation storage function between the hardware redirector (for fast access) and the usage history table (for persistent LRU tracking). This allows the hardware redirector to maintain a compact size while the system achieves high hit rates through the coordinated operation of both structures. The usage history table effectively extends the capacity without proportionally increasing the critical hardware redirector area.
4Quantity of substance
If translations are frequently evicted from the hardware redirector to manage memory, then hardware structure capacity is maintained, but access time increases when translations must be re-fetched
Solution Approach 1:
The system performs preliminary action by maintaining LRU usage history information in the usage history table before translations are needed again. When a translation is evicted from the hardware redirector, its usage pattern is already recorded, enabling the system to quickly restore it from the usage history table rather than requiring a time-consuming re-generation or extensive search process. This preliminary tracking minimizes the time loss associated with eviction and re-fetching.
Data Source
AI summary
In one embodiment, a micro-processing system includes a hardware structure disposed on a processor core. The hardware structure includes a plurality of entries, each of which are associated with portion of code and a translation of that code which can be executed to achieve substantially equivalent functionality. The hardware structure includes a redirection array that enables, when referenced, execution to be redirected from a portion of code to its counterpart translation. The entries enabling such redirection are maintained within or evicted from the hardware structure based on usage information for the entries.