Hardware Synchronous Engine for Multiprocessor Atomic Operations
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Solution Overview
Problem
Existing software-based synchronization primitives in parallel programs face inefficiencies such as high start costs, slow execution speeds, and excessive inter-process communication, particularly due to the need for atomic operations and cache coherence management, which hinder processor performance.
Innovation Solution
A hardware-based synchronous engine device with storage queues, scheduling modules, processing modules, and a virtual synchronous memory structure that uses a unified shared memory to execute synchronization primitives like Barrier, Lock, and Reduce, ensuring atomicity and reducing communication bandwidth usage, independent of cache coherence and special instructions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software-based synchronization primitives are used to ensure atomic operations and cache coherence, then synchronization correctness is maintained, but execution speed decreases and communication bandwidth is excessively occupied
Solution Approach 1:
The patent replaces software-based synchronization mechanisms with a hardware-based synchronous engine device. This device includes storage queues for receiving synchronization requests, processing modules for executing synchronization operations, and a unified shared memory structure for data storage. By implementing synchronization primitives (Barrier, Lock, Reduce) in hardware rather than software, the system achieves both atomic operation guarantees and high execution speed, eliminating the performance penalty of software-based approaches while maintaining synchronization correctness
Solution Approach 2:
The patent introduces a dedicated synchronous engine device as an intermediary between processors and shared memory. This device acts as a mediator that handles all synchronization operations, including Barrier synchronization, Lock/Unlock operations, and Reduce calculations. The synchronous engine receives synchronization requests from multiple processors, processes them through specialized hardware modules, and manages the unified shared memory structure, thereby offloading synchronization overhead from processors and improving overall system execution speed
2Reliability
If software-based synchronization primitives are used with shared counters and loop reading, then synchronization coordination is achieved, but start cost increases and communication bandwidth is excessively occupied
Solution Approach 1:
The patent replaces software-based synchronization with a hardware-implemented synchronous engine that processes synchronization operations in parallel. The storage queues accept synchronization requests from multiple processors simultaneously, and the processing modules execute Barrier, Lock, and Reduce operations using dedicated hardware circuits rather than sequential software loops. This eliminates the high start cost and time consumption associated with software-based approaches while maintaining reliable synchronization coordination
Solution Approach 2:
The patent implements a unified shared memory structure that is pre-configured and managed by the synchronous engine before synchronization operations begin. The storage queues are pre-established to receive synchronization requests, and the memory structure is prepared to store and retrieve data for Barrier, Lock, and Reduce operations. This preliminary setup eliminates the need for runtime memory allocation and initialization that contributes to high start costs in software-based approaches
Data Source
AI summary
The invention discloses a multiprocessor System and synchronous engine device thereof. the synchronous engine includes: a plurality of storage queues, wherein one of the queues stores all synchronization primitives from one of the processors; a plurality of scheduling modules, selecting the synchronization primitives for execution from the plurality of storage queues and then according to the type of the synchronization primitive transmitting the selected synchronization primitives to corresponding processing modules for processing, scheduling modules corresponding in a one-to-one relationship with the storage queues; a plurality of processing modules, receiving the transmitted synchronization primitives to execute different functions; a virtual synchronous memory structure module, using small memory space and mapping main memory spaces of all processors into a synchronization memory structure to realize the function of all synchronization primitives through a control logic; a main memory port, communicating with virtual synchronous memory structure module to read and write the main memory of all processors, and initiate an interrupt request to processors; a configuration register, storing various configuration information required by processing modules.