Hardware Verification Abstraction Model for State Explosion
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Solution Overview
Problem
The challenge in formal verification of complex hardware designs, such as microprocessors, lies in the exponential growth of the state space due to increasing complexity and size, leading to an untractable verification gap, particularly in verifying control logic and datapath units, which requires efficient methodologies tailored to different structural patterns and abstraction levels.
Innovation Solution
A system and method for verifying hardware designs that involve providing a hardware design description, extracting design constraints, creating an abstraction model by replacing logical operations with uninterpreted functions, and property checking, with refinement of the abstraction model when violations are detected, to facilitate tractable verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If formal verification exhaustively examines the entire design state space, then verification correctness is improved, but computational complexity grows exponentially
Solution Approach 1:
The verification system segments the design into control logic and datapath units, applying different verification methodologies to each. Control logic is verified using theorem provers with mathematical models, while datapath units are verified separately exploiting their structural regularity. This segmentation reduces the overall verification complexity by breaking down the exponentially large state space into manageable portions.
Solution Approach 2:
The system introduces abstraction models as intermediaries between the RTL description and the verification process. These mathematical models simplify the datapath while preserving control logic behavior, serving as a mediator that reduces verification complexity. The abstraction models allow theorem provers to reason about control logic without being overwhelmed by datapath complexity.
2Productivity
If verification methodologies are tailored to different structural patterns, then verification effectiveness is improved, but methodology complexity increases
Solution Approach 1:
The verification system applies local quality by using different verification approaches for different parts of the design based on their structural characteristics. Datapath units with regular structures receive specialized verification exploiting their patterns, while control logic receives theorem-proving-based verification. This localized approach optimizes verification effectiveness for each structural type without requiring a single complex methodology for the entire design.
3Measurement precision
If manual model regeneration is performed from RTL, then verification accuracy is improved, but time consumption increases
Solution Approach 1:
The system implements self-service by automatically regenerating verification models from RTL descriptions using programmatic transformations. The abstraction models are generated automatically from the RTL code through systematic processes that preserve accuracy while eliminating manual intervention. This automated model generation maintains verification accuracy while dramatically reducing the hundreds of man-hours previously required.
Data Source
AI summary
A system and methods are provided for verifying a hardware design for an electronic circuit. The method may include: providing a hardware design description for the electronic circuit; extracting a set of design constraints from the hardware design description, where the set of design constraints represents the electronic circuit in terms of signals and logical operations performed on the signals; creating an abstraction model from the set of design constraints, where the abstraction model abstracts one or more of the logical operations in the set of design constraints by replacing the abstracted logical operations with uninterpreted functions; and property checking the abstraction model in relation to one or more design properties. When a violation in the electronic circuit is detected by the property checking step, the feasibility of the violation is then checked and, if the violation is deemed infeasible, the abstraction model is refined.