HBM Base Die Signal Sharing Across Memory Stacks

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Solution Overview

Problem

High-bandwidth memory devices face challenges in optimizing electrical characteristics due to the inefficiencies in data signal transmission and power supply distribution across multiple memory stacks, leading to potential issues with data access and power allocation.

Innovation Solution

A memory device design that includes a base die with data signal bumps shared by multiple memory stacks, allowing selective data signal distribution based on selection signals, and utilizing residual bumps for power supply and adhesion, thereby improving power characteristics and reducing redundant signal transmission infrastructure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate data signal transmission paths are provided for each memory stack, then data access reliability is improved, but device complexity and manufacturing cost increase

Engineering Contradiction:
Improvedata access reliabilityVSAvoidsignal transmission infrastructure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges separate data signal transmission paths into a shared transmission path that serves multiple memory stacks. A single data signal bump is used to transmit data signals to multiple memory stacks through a multiplexer, reducing the number of transmission paths while maintaining reliable data access through selective routing.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The data signal bump and transmission path are designed to serve multiple functions by supporting data transmission to multiple different memory stacks. The multiplexer enables the same physical path to be dynamically allocated to different stacks based on access requirements, making the infrastructure universal rather than dedicated.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If dedicated power supply paths are provided for each memory stack, then power distribution reliability is improved, but device complexity and manufacturing cost increase

Engineering Contradiction:
Improvepower distribution reliabilityVSAvoidpower supply infrastructure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines multiple dedicated power supply paths into a shared power supply path that serves multiple memory stacks. Power signals are transmitted through common power supply bumps and distributed to different stacks as needed, reducing infrastructure complexity while maintaining reliable power delivery through the shared path design.

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If multiple data signal bumps are used for multiple memory stacks, then data transmission efficiency is improved, but manufacturing cost and device complexity increase

Engineering Contradiction:
Improvedata transmission efficiencyVSAvoidnumber of bumps
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent makes the data signal bump universal by enabling it to serve multiple memory stacks through a multiplexer. A single data signal bump performs the function of what would traditionally require multiple dedicated bumps, reducing the total number of bumps while maintaining efficient data transmission capability through dynamic path selection.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentEP4376002A1Memory device and system device including the same
Publication Date: 2024.05.29 SAMSUNG ELECTRONICS CO LTD
  • EP4376002A1 patent drawingFigure 1
  • EP4376002A1 patent drawingFigure 2
  • EP4376002A1 patent drawingFigure 3

AI summary

A memory device includes a base die that includes a data signal bump configured to receive a data signal, a first memory stack that includes first memory dies sequentially stacked on the base die, and a second memory stack that includes second memory dies sequentially stacked on the base die and spaced from the first memory stack in a direction parallel to an upper surface of the base die. The base die is configured to selectively provide the data signal received through the data signal bump to one of the first memory stack or the second memory stack based on a selection signal.