HBM Memory Module Layout for Uniform Signaling and Stable Power
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Solution Overview
Problem
The challenge in high bandwidth memory (HBM) structures is the increasing communication delay and power supply instability as the number of stacked layers increases, affecting operating speed and reliability.
Innovation Solution
A semiconductor structure with memory chips stacked parallel to the substrate surface, featuring power supply wiring layers that lead out power supply signal lines, solder bumps for secure connections, and lead frames for specifying power paths, ensuring uniform communication distances and stable power supply.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked memory chip layers is increased to improve memory capacity and bandwidth, then the memory density and capacity are improved, but the communication delay increases and operating speed deteriorates
Solution Approach 1:
The patent transitions from a traditional vertical stacking architecture to a horizontal stacking architecture where memory chips are arranged parallel to the substrate surface. This dimensional change allows memory chips to be stacked in the first direction (parallel to substrate) rather than vertically, reducing communication distance and delay while maintaining high density through the lead frame's extended structure.
Solution Approach 2:
The lead frame serves as an intermediary component that connects horizontally arranged memory chips to the substrate. It provides both mechanical support and electrical connection, enabling the memory chips to be positioned in a configuration that optimizes communication speed while maintaining high capacity through the extended lead frame structure.
2Quantity of substance
If the number of stacked memory chip layers is increased to improve memory capacity, then the memory density is improved, but power supply stability deteriorates
Solution Approach 1:
The power supply wiring layer is configured to lead out power supply signal lines from the memory chips in a horizontal arrangement. This dimensional reconfiguration allows for optimized power distribution paths that reduce interference and improve stability compared to vertical stacking, where power signals would have to traverse longer vertical distances through multiple chip layers.
Solution Approach 2:
The power supply system is segmented into dedicated wiring layers that are separately configured for each memory chip. This segmentation allows independent optimization of power supply paths for each chip, reducing cumulative interference and improving overall power supply stability in the horizontal stacking configuration.
3Quantity of substance
If memory chips are stacked vertically to improve memory capacity, then the memory density is improved, but communication uniformity deteriorates due to varying communication distances
Solution Approach 1:
The patent arranges memory chips horizontally parallel to the substrate surface rather than stacking them vertically. This dimensional change ensures that all memory chips are at approximately the same distance from the substrate and from each other, creating uniform communication paths. The lead frame extends horizontally to connect all chips, maintaining consistent signal transmission characteristics across all memory elements.
Solution Approach 2:
The horizontal arrangement of memory chips creates an equipotential configuration where all chips experience similar communication conditions and distances to the substrate and control logic. This eliminates the gradient effect present in vertical stacking, where chips at different heights experience different communication delays and signal integrity.
Data Source
AI summary
Embodiments provide a semiconductor structure and a fabricating method. The semiconductor structure includes: a substrate having a power supply port; a memory module positioned on an upper surface of the substrate, where the memory module includes memory chips stacked in a first direction, the first direction is parallel to the upper surface of the substrate, each of the memory chips has a power supply signal line, at least one of the memory chips has a power supply wiring layer, the power supply signal line is electrically connected to the power supply wiring layer, the power supply wiring layer is positioned in the memory module, an end surface of the power supply wiring layer far away from the substrate is exposed by the memory module, and a solder bump is further provided on the end surface; and a lead frame electrically connected to the solder bump and the power supply port.