Head-Core Program Forwarding for Lower-Power Multi-Core Processing
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Solution Overview
Problem
Existing data processing chips face challenges in efficiently utilizing computing power due to inefficient task scheduling and allocation, leading to high power consumption and reduced performance, especially in multi-core or many-core architectures.
Innovation Solution
A data processing apparatus with a preset execution sequence among processing cores, where the head processing core sends instructions and programs to subsequent cores, eliminating the need for each core to read from external memory, thereby reducing power consumption and optimizing task execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If each processing core reads data from external memory separately, then each core can independently execute programs, but power consumption increases and data exchange delays occur
Solution Approach 1:
Multiple processing cores share a common program memory resource instead of each core having separate memory access. The heads core reads programs from external memory and passes them to subsequent cores in the execution sequence, merging memory access operations into a single shared resource that serves all cores.
Solution Approach 2:
The head processing core acts as an intermediary between external memory and other processing cores. It retrieves programs from external memory and distributes them to subsequent cores through internal data buses, eliminating the need for other cores to directly access external memory.
2Ease of operation
If multiple processing cores access external memory simultaneously, then each core can execute independent programs, but data exchange delays increase
Solution Approach 1:
The head processing core preliminarily retrieves programs from external memory before other cores need them. Programs are fetched in advance and passed along the execution sequence, so that when subsequent cores need to execute programs, they already reside in internal buffers ready for immediate processing.
Solution Approach 2:
The system segments program execution into distinct phases: the head core handles external memory access and program retrieval, while subsequent cores handle program execution and passing to the next core. This segmentation separates memory access operations from execution operations, reducing simultaneous access conflicts.
3Productivity
If complex parallel circuits are used to enable parallel execution, then computing power is enhanced, but device complexity increases
Solution Approach 1:
Instead of creating complex parallel circuit paths for each core to access memory independently, the system uses a simpler approach where the head core copies programs from external memory and distributes them to subsequent cores through standardized internal data buses. This copying mechanism achieves parallel execution without requiring complex parallel memory access circuits.
Data Source
AI summary
Disclosed is a data processing apparatus, chip, and data processing method. The data processing apparatus includes: a plurality of processing cores having a preset execution sequence, the plurality of processing cores including a head processing core and at least one other processing core; wherein the head processing core is configured to send an instruction, and receive and execute a program obtained according to the instruction; and each of the other processing cores is configured to receive and execute a program sent by a previous processing core in the preset execution sequence.