Heat Dissipation Multilayer for Phonon-Mismatched C-FET Stacks
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Solution Overview
Problem
Existing complementary field effect transistors (C-FET) structures face challenges with high thermal boundary resistance due to phonon frequency mismatch at the interfaces of different high-kappa materials, which affects heat dissipation in stacked device configurations.
Innovation Solution
Incorporation of a dielectric layer with an amorphous structure as a bridging layer between high-kappa layers in a heat dissipation multilayer to reduce thermal boundary resistance, improving heat dissipation by facilitating phonon transmission across materials with different phonon frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If high-kappa materials are used in stacked C-FET structures, then device performance is improved, but thermal boundary resistance increases due to phonon frequency mismatch
Solution Approach 1:
An intermediary layer with intermediate phonon frequency is introduced between high-kappa materials with mismatched phonon frequencies. This intermediary layer acts as a mediator that facilitates phonon transmission across the interface, reducing thermal boundary resistance while allowing the high-kappa materials to maintain their performance-enhancing properties
Solution Approach 2:
The patent employs composite material structures combining multiple layers with different phonon frequency characteristics. By creating a composite thermal management structure that includes materials with graded phonon frequencies, the system achieves both high device performance and effective heat dissipation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dielectric layer effectively reduces thermal boundary resistance, enhancing heat dissipation between stacked transistors and improving overall thermal performance of the semiconductor device.
Implementation Method 1
a first heat dissipation layer, a second heat dissipation layer, and a dielectric layer between the first heat dissipation layer and the second heat dissipation layer, in which the first heat dissipation layer has a first range of phonon frequency, the second heat dissipation layer has a second range of phonon frequency distinct from the first range of phonon frequency, and the dielectric layer has a third range of phonon frequency overlapping the first range of phonon frequency and the second range of phonon frequency
Data Source
AI summary
Method to implement heat dissipation multilayer and reduce thermal boundary resistance for high power consumption semiconductor devices is provided. The heat dissipation multilayer comprises a first crystalline layer that possesses a first phonon frequency range, a second crystalline layer that has a second phonon frequency range which does not overlap with the first phonon frequency range, and an amorphous layer located between the first and second crystalline layers. The amorphous layer has a third phonon frequency range that overlaps both the first and second phonon frequency ranges.