Helium-Doped Isolation Oxide for Low-Stress Active Patterns
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Solution Overview
Problem
Current semiconductor device fabrication methods face challenges in forming a densified device isolation layer that effectively reduces stress on active patterns and maintains junction isolation properties, particularly when dealing with high aspect ratio trenches and high temperature annealing processes.
Innovation Solution
A method involving a preliminary insulating layer filled with a light species such as helium, subjected to hot ion implantation and wet annealing, to form a silicon oxide layer that completely oxidizes and densifies the device isolation layer, reducing stress on active patterns and preventing deformation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high temperature annealing is used to densify the device isolation layer, then the oxide layer becomes more dense and junction isolation is improved, but stress on active patterns increases causing deformation
Solution Approach 1:
The method introduces a preliminary insulating layer formation step before the annealing process. This preliminary layer is specifically designed to compensate for stress that will develop during subsequent high-temperature annealing, preventing deformation of active patterns while allowing the oxide layer to densify for improved junction isolation
Solution Approach 2:
The method changes the physical and chemical parameters of the isolation layer by doping it with light species (H, He, C, N, O, Ar, Kr, or Xe) at controlled concentrations. This modification allows the layer to achieve densification and improved isolation properties during annealing while maintaining stress compensation capabilities
2Reliability
If the device isolation layer is made denser to reduce etch rates, then junction isolation properties are maintained, but the formation process becomes more complex
Solution Approach 1:
The method combines multiple functions into the device isolation layer formation process: the preliminary insulating layer is formed with specific material composition and doping that simultaneously provides stress compensation, etch rate control, and junction isolation. The annealing process then achieves densification while maintaining these combined properties, reducing the need for separate process steps
Solution Approach 2:
By controlling the doping concentration of light species in the preliminary insulating layer and optimizing annealing parameters, the method achieves the desired dense oxide layer with controlled etch rates. The specific parameter ranges (doping concentration, annealing temperature, ion implantation energy) are optimized to achieve densification without requiring additional complex process steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach results in a semiconductor device with improved electric characteristics and reduced etch rates, maintaining junction isolation properties while preventing deformation of active patterns and achieving a defect-free oxide layer.
Implementation Method 1
performing a first ion implantation process to inject a light species into the preliminary insulating layer
Implementation Method 2
performing a wet annealing process on the preliminary insulating layer
Implementation Method 3
the device isolation layer including a silicon oxide layer doped with helium, a helium concentration of the device isolation layer being higher than a helium concentration of the first and second active patterns
Data Source
AI summary
A semiconductor device includes a substrate including a first active pattern and a second active pattern, a device isolation layer filling a first trench between the first and second active patterns, the device isolation layer including a silicon oxide layer doped with helium, a helium concentration of the device isolation layer being higher than a helium concentration of the first and second active patterns, and a gate electrode crossing the first and second active patterns.