Passive Helium Convection Loop for Flat Cryogenic Wafer Cooling

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Solution Overview

Problem

Existing wafer testing systems face challenges in maintaining a flat wafer geometry and achieving effective heat sinking and alignment in low-pressure or vacuum environments, particularly when testing superconducting and low-temperature circuitry, due to limitations in thermal conductance and wafer deformation.

Innovation Solution

A system utilizing a helium convection loop with a passive helium convection loop and welded flexible bellows hoses, combined with a wafer holding structure comprising two separable portions, one for securement and the other for heat sinking, ensures effective thermal contact and alignment without wafer deformation, even in vacuum conditions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Stability of the object's composition

If conventional wafer holding methods are used in vacuum environment, then wafer can be secured, but wafer geometry becomes deformed and thermal contact is insufficient

Engineering Contradiction:
Improvewafer geometry stabilityVSAvoidthermal contact quality
Core Design Contradiction:
Stability of the object's compositionVSReliability

Solution Approach 1:

The wafer holding system is divided into two separate components: a holder that provides mechanical support and a chuck that provides thermal contact. This segmentation allows each component to be optimized for its specific function without compromising the other, resolving the contradiction between maintaining wafer geometry stability and ensuring adequate thermal contact.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A CTE-matched interface layer is introduced between the holder and the chuck to serve as an intermediary. This intermediary layer compensates for thermal expansion differences and maintains reliable thermal contact in vacuum environments, solving the contradiction by mediating between mechanical support requirements and thermal contact requirements.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Force

If gas pressure is used to provide compressive contact force to wafer, then wafer can be held securely, but method fails in vacuum or low-pressure environments

Engineering Contradiction:
Improvecompressive contact forceVSAvoidenvironmental adaptability
Core Design Contradiction:
ForceVSAdaptability or versatility

Solution Approach 1:

The gas pressure-based mechanical system is replaced with a spring-based mechanical system. The spring-loaded mechanism provides compressive contact force through elastic deformation, which is independent of environmental pressure conditions. This substitution enables the system to function reliably in both vacuum and atmospheric environments.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The operating parameters of the wafer holding system are changed from pressure-dependent to force-dependent. By using springs with specific force constants and pre-load settings, the system achieves environment-independent operation. The spring force remains effective whether the external pressure is atmospheric or vacuum conditions.

Inventive Principle:
Principle #35Parameter changes

3Force

If wafer clamping approach is used in vacuum, then wafer can be secured, but heat sinking occurs only at edge or central regions due to wafer bending

Engineering Contradiction:
Improvewafer clamping forceVSAvoidheat sinking distribution
Core Design Contradiction:
ForceVSTemperature

Solution Approach 1:

The wafer holding system is segmented into a holder for mechanical support and a chuck for thermal contact. This separation ensures that the chuck can be positioned to contact the wafer at multiple points (edge and center) simultaneously, providing uniform heat sinking across the entire wafer surface rather than concentrating thermal contact at a single location.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The thermal contact approach transitions from a single-point or edge-only contact to a distributed multi-point contact across the wafer surface. By positioning the chuck to engage the wafer at multiple locations simultaneously, the system achieves two-dimensional heat sinking distribution, effectively cooling the entire wafer rather than just peripheral or central regions.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The system maintains a flat wafer geometry and provides efficient heat sinking and alignment, enabling reliable testing of superconducting and low-temperature circuitry at the wafer level, with improved thermal conductance and reduced mechanical stress.

Implementation Method 1

A two-phase helium convection loop is coupled to the heat sink

Methodology Applied
Scientific EffectTwo-phase flow: Two-Phase Flow

Implementation Method 2

helium convection loop

Methodology Applied
Scientific EffectConvection: Convection

Implementation Method 3

CTE-matched wafer holder

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS12631682B2Two-phase helium convection loop for cryogenic cooling
Publication Date: 2026.05.19 MASSACHUSETTS INST OF TECH
  • US12631682B2 patent drawing
  • US12631682B2 patent drawing
  • US12631682B2 patent drawing

AI summary

Described is a probing system and technique for testing superconducting and low-temperature circuitry at the wafer level. In embodiments, the system includes a helium convection loop such as a passive helium convection loop. The use of a passive helium convection loop enables the use of welded flexible bellows hoses. Also described is a wafer holding structure having a fixed portion configured to be removably secured to a wafer to be tested and a second portion configured to be removably secured to the fixed portion and configured to remain in a testing chamber portion of a wafer probing system and configured to provide force application and alignment functionality to a wafer to be tested.