HEMT and 2DEG Resistor Integration for Compact Semiconductor Layouts

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Solution Overview

Problem

Existing semiconductor devices require separate integration of high electron mobility transistors (HEMTs) and resistors, leading to a large footprint and complex fabrication due to discrete components.

Innovation Solution

Integrating a high electron mobility transistor and a resistor on a single chip by utilizing a two-dimensional electron gas (2DEG) generated by a stacked compound semiconductor structure, with an intermediate electrode allowing resistance adjustment through applied negative biases.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If discrete components are used for resistor and HEMT, then the circuit can be assembled, but the footprint area becomes large and fabrication becomes complex

Engineering Contradiction:
Improvefabrication complexityVSAvoidfootprint area
Core Design Contradiction:
Ease of manufactureVSArea of stationary object

Solution Approach 1:

The patent merges the resistor and HEMT onto a single semiconductor chip, integrating what were previously discrete components. The resistor is formed using the 2DEG layer in the passive element region while the HEMT is formed in the active element region, eliminating the need for separate components and reducing overall footprint area.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The 2DEG layer serves dual purposes: it forms the active channel region for the HEMT transistor and simultaneously creates the resistive element. This multi-functionality allows a single structural feature to fulfill multiple circuit functions, simplifying fabrication and reducing component count.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If a variable resistor is needed with different resistance values, then the circuit requirements can be met, but additional process steps or structure changes are required

Engineering Contradiction:
Improveresistance adjustment capabilityVSAvoidstructure complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements a variable resistor by applying different negative biases to the intermediate electrode, which dynamically adjusts the resistance value. The resistance can be tuned from high resistance (when negative bias is applied to deplete 2DEG) to low resistance (when no bias or positive bias is applied), all within the same fixed structure without requiring physical reconfiguration.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The resistance value is adjusted by changing the electrical parameter (bias voltage) applied to the intermediate electrode rather than changing the physical structure. By varying the negative bias voltage, the 2DEG concentration in the channel region changes, which directly controls the resistance value without requiring structural modifications.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This integration reduces the layout area and manufacturing cost of semiconductor devices while meeting the resistance requirements of various resistors without altering the device structure or size, enabling variable resistance without additional process steps.

Implementation Method 1

A two-dimensional electron gas (2DEG) generated by a stacked structure of a compound semiconductor channel layer and a compound semiconductor barrier layer

Methodology Applied
Scientific EffectTwo-dimensional electron gas (2DEG):

Implementation Method 2

Through applying different negative biases to the intermediate electrode, the resistance of the resistor is adjusted

Methodology Applied
Scientific EffectElectrical resistance control through biasing: Electrical Resistance

Data Source

PatentUS12588272B2Semiconductor device
Publication Date: 2026.03.24 VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
  • US12588272B2 patent drawing
  • US12588272B2 patent drawing
  • US12588272B2 patent drawing

AI summary

A semiconductor device includes a compound semiconductor channel layer disposed on a substrate and located in an active element region and a passive element region. A compound semiconductor barrier layer is stacked on the compound semiconductor channel layer and located in the active element region and the passive element region. A source electrode, a gate electrode and a drain electrode are disposed on the compound semiconductor barrier layer and located in the active element region to construct a high electron mobility transistor. In addition, a first terminal electrode, an intermediate electrode and a second terminal electrode are disposed on the compound semiconductor barrier layer and located in the passive element region to construct a resistor.