GaN HEMT Alignment Layer Layout for Normally-Off Low-Leakage Operation
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Solution Overview
Problem
The development of high electron mobility transistors (HEMTs) using gallium nitride on sapphire substrates faces challenges with increased substrate area and manufacturing costs, as well as high leakage current and normally-on type characteristics due to conductive alignment layers.
Innovation Solution
A transistor design utilizing an amorphous substrate with a conductive alignment layer, a heterojunction structure, and a recessed polarization layer to reduce leakage current and achieve normally-off type characteristics by controlling the c-axis orientation of the semiconductor layer and weakening the piezoelectric effect in the region overlapping the gate electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conductive alignment layer is used to control c-axis orientation of the semiconductor layer, then the crystallinity and orientation control are improved, but the leakage current increases and normally-on type characteristics are generated
Solution Approach 1:
The alignment layer is divided into two distinct layers: an insulating alignment layer (first alignment layer) for c-axis orientation control, and a conductive alignment layer (second alignment layer) positioned only in source/drain regions. This segmentation allows the insulating layer to prevent leakage current while the conductive layer provides necessary orientation control where needed.
Solution Approach 2:
An insulating alignment layer is introduced as an intermediary between the substrate and the conductive alignment layer. This insulating layer acts as a mediator that blocks leakage current paths while allowing the conductive alignment layer to maintain its orientation-control function in the source/drain regions without causing harmful leakage effects.
2Area of moving object
If the substrate area is increased to accommodate larger transistor devices, then the device performance is improved, but the manufacturing cost increases
Solution Approach 1:
The conductive alignment layer is applied locally only in the source and drain regions rather than across the entire substrate or channel region. This localized application reduces material consumption and processing complexity, thereby lowering manufacturing costs while still achieving the necessary c-axis orientation control in the critical source/drain areas.
3Quantity of substance
If the piezoelectric effect is strengthened to increase charge density at the heterojunction interface, then the two-dimensional electron gas concentration is improved, but the short channel effect increases
Solution Approach 1:
The piezoelectric effect is activated locally only in the source and drain regions through the conductive alignment layer, while the channel region maintains moderate electron gas concentration. This spatial differentiation allows high charge density where needed for carrier injection while preventing excessive piezoelectric fields in the channel that would cause short channel effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively suppresses leakage current and reduces the short channel effect, maintaining high crystallinity and voltage resistance while ensuring the transistor operates in a normally-off enhancement mode.
Implementation Method 1
charges are induced by the spontaneous polarization of the gallium nitride film in the semiconductor layer and the piezoelectric effect of the aluminum gallium nitride in the polarization layer
Implementation Method 2
charges are induced by the spontaneous polarization of the gallium nitride film in the semiconductor layer and the piezoelectric effect of the aluminum gallium nitride in the polarization layer
Data Source
AI summary
A transistor according to an embodiment of the present invention includes an amorphous substrate, a conductive alignment layer over the amorphous substrate, a heterojunction structure including a semiconductor layer and a polarization layer in contact with the semiconductor layer over the conductive alignment layer, and a gate electrode over the heterojunction structure. The heterojunction structure comprises a recessed portion in a region overlapping the gate electrode. The recessed portion may be provided in the polarization layer or the semiconductor layer.