HEMT Qualification Using Dual Pulse Generators
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The qualification of high electron mobility transistors (HEMTs), such as GaN FET devices, is challenging due to complex hole and electron trapping characteristics and current collapse behaviors, requiring time-consuming and expensive testing processes that often result in wasted resources when devices fail to meet specifications.
Innovation Solution
A novel test method using dual pulse generators applied to wafer probes to simulate various load conditions on GaN FET devices, allowing for non-overlapping and overlapping voltage pulses to assess drain current under different switching conditions, enabling efficient qualification without custom hardware and reducing waste by testing at the wafer scale.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If dedicated custom test environment and circuit boards are used to qualify HFET devices, then measurement precision is improved, but device complexity and loss of time increase
Solution Approach 1:
The patent uses standard off-the-shelf pulse generators and measurement equipment instead of custom-built test equipment. By copying the essential test functions using commercially available components, the system achieves the required measurement precision while dramatically reducing test setup time and complexity.
Solution Approach 2:
The test method employs universal, multi-functional equipment that can perform multiple qualification tests. The standard pulse generators and oscilloscopes used can be configured for different test conditions (soft switching, hard switching, various pulse widths), eliminating the need for dedicated custom circuit boards for each test type.
2Reliability
If comprehensive qualification testing is performed on packaged devices, then reliability is improved, but loss of substance increases due to wasted packaging materials
Solution Approach 1:
The patent performs qualification testing at the wafer level before the devices are packaged. By conducting soft switching and hard switching tests on the wafer using standard equipment, the system identifies defective devices early, preventing waste of packaging materials (solder balls, wires, mold compound, epoxies) on devices that would fail qualification anyway.
Solution Approach 2:
The testing process extracts the qualification function from the packaged device context and performs it at the wafer level. This separation allows testing to occur before packaging, eliminating the waste of packaging materials on failed devices while maintaining comprehensive qualification coverage.
3Measurement precision
If complex testing procedures are used to assess carrier trapping and current collapse, then measurement precision is improved, but device complexity and cost increase
Solution Approach 1:
The patent replicates the complex physical test conditions (soft switching, hard switching, various pulse widths and frequencies) using standard, off-the-shelf pulse generators and measurement equipment. This copying approach achieves the required measurement precision for carrier trapping and current collapse assessment without requiring complex custom-built test systems.
Solution Approach 2:
The test method varies parameters (pulse width, frequency, voltage levels) using standard equipment to probe different aspects of carrier trapping and current collapse behavior. By changing operational parameters rather than changing the fundamental test equipment, the system achieves comprehensive measurements while keeping device complexity low.
Data Source
AI summary
A method includes coupling a gate pulse generator to a gate terminal of a power transistor device under test, coupling a drain pulse generator to a drain terminal of the power transistor device under test; for a first set of test conditions, activating the drain pulse generator for each of the test conditions to apply a voltage pulse to the drain terminal, and for each of the test conditions, applying a voltage pulse to the gate terminal, the gate pulse rising only after the drain pulse falls below a predetermined threshold; for a second set of test conditions, applying a voltage pulse to the drain terminal, and applying a voltage pulse to the gate terminal, the drain pulse generator and the gate pulse generator both being active so that there is some overlap; and measuring the drain current into the power transistor device under test. An apparatus is disclosed.