HEMT Gate Electrode Under Channel for Quantum Noise Reduction

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Solution Overview

Problem

Low-noise amplifiers (LNAs) in quantum computing systems face a trade-off between power consumption and noise properties, with high power consumption leading to excess heat and accuracy issues, limiting the scalability of quantum computers due to the degradation of noise temperature caused by access resistance and parasitic capacitance in traditional HEMT transistor designs.

Innovation Solution

A high-electron-mobility transistor (HEMT) structure is optimized by placing the gate electrode underneath the channel, reducing access resistance and parasitic capacitance, achieved by coupling the source and drain electrodes to the top surface and positioning the gate electrode on the underside of the HEMT heterostructure, along with encapsulating the gate electrode and interconnect to minimize noise temperature degradation at low power levels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the gate electrode is placed on the top surface of the HEMT heterostructure (traditional configuration), then the device structure is simpler and easier to manufacture, but the access resistance and parasitic capacitance increase, causing degradation of noise temperature

Engineering Contradiction:
Improveease of manufactureVSAvoidnoise temperature degradation
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The gate electrode is inverted from its traditional position on the top surface to the bottom surface of the HEMT heterostructure. This inversion allows the gate to control the channel from underneath, reducing the access resistance and parasitic capacitance that plague traditional top-gate configurations, thereby improving noise temperature performance

Inventive Principle:
Principle #13The other way round (Inversion)

2Power

If the HEMT operates at high power consumption, then the signal amplification is stronger, but the waste heat increases and noise temperature degrades, limiting quantum system scalability

Engineering Contradiction:
Improvesignal amplification strengthVSAvoidwaste heat
Core Design Contradiction:
PowerVSLoss of energy

Solution Approach 1:

By changing the physical configuration parameters of the HEMT (specifically the gate electrode position from top to bottom), the device achieves improved electrical characteristics with lower access resistance and parasitic capacitance. This allows the amplifier to operate effectively at lower power consumption levels, reducing waste heat generation while maintaining signal amplification capability

Inventive Principle:
Principle #35Parameter changes

3Reliability

If the access resistance and parasitic capacitance are reduced through structural optimization, then the noise temperature degradation decreases, but the device structure becomes more complex

Engineering Contradiction:
Improvenoise temperature performanceVSAvoidstructural complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The inversion of the gate electrode to the bottom surface simultaneously achieves multiple goals: it reduces access resistance by creating a more direct electrical path, decreases parasitic capacitance by increasing separation between the gate and source/drain regions, and maintains manufacturing feasibility through standard semiconductor fabrication processes

Inventive Principle:
Principle #13The other way round (Inversion)

Data Source

PatentUS20230197842A1High electron mobility transistor with gate electrode below the channel
Publication Date: 2023.06.22 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US20230197842A1 patent drawing
  • US20230197842A1 patent drawing
  • US20230197842A1 patent drawing

AI summary

One or more systems, devices, methods of use and/or methods of fabrication provided herein relate to a high-electron-mobility transistor with a gate electrode below the channel. According to one embodiment, a device comprises a source electrode and a drain electrode coupled to a top surface of a high-electron-mobility transistor (HEMT) heterostructure, and a gate electrode located in contact with an underside of the HEMT heterostructure