HEMT Source Field Plate for Nitride Semiconductor Field Relaxation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor devices with HEMT structures face challenges in reducing parasitic capacitance and relaxing electric field concentration on the ends of gate electrodes, which affects high-speed and high-frequency operations.
Innovation Solution
A semiconductor device with a Group III nitride semiconductor lamination structure, including a source field plate embedded in the insulating layer between the gate and drain electrodes, which is self-aligned during manufacturing, allowing for precise control of the distance between the gate electrode and the source field plate through the thickness of the gate insulating film, thereby reducing parasitic capacitance and electric field concentration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a gate field plate is formed to relax electric field concentration on the gate electrode end portion, then electric field concentration is reduced, but parasitic capacitance increases due to the larger structure required
Solution Approach 1:
An insulating film is introduced as an intermediary between the gate electrode and the source field plate. This insulating film allows the source field plate to relax electric field concentration on the gate electrode end portion while preventing direct electrical connection that would create parasitic capacitance. The insulating film acts as a mediator that enables the beneficial field-relaxing effect while blocking the harmful capacitance formation.
Solution Approach 2:
The structure is segmented by dividing the field plate function into two separate components: a gate field plate for relaxing electric field at the gate end and a source field plate for relaxing electric field at the source end. These are electrically isolated from each other through the insulating film, allowing independent optimization of each field plate's function while minimizing total parasitic capacitance.
2Object-affected harmful factors
If the distance between the gate electrode and source field plate is reduced to improve field relaxation, then electric field concentration is reduced, but manufacturing precision becomes more difficult to control
Solution Approach 1:
The source field plate is configured to self-align with the gate electrode through the insulating film structure. The insulating film serves as a self-aligning spacer that automatically establishes the optimal distance between the gate electrode and source field plate during the formation process, eliminating the need for complex alignment procedures and ensuring consistent spacing.
Solution Approach 2:
The insulating film is formed beforehand between the gate electrode and source field plate before final positioning. This preliminary formation of the insulating layer establishes a predetermined spacing that guides subsequent alignment steps, ensuring that the source field plate is positioned at the correct distance from the gate electrode without requiring high-precision direct alignment.
3Object-affected harmful factors
If a source field plate is added to relax electric field concentration, then electric field distribution is improved, but device complexity increases
Solution Approach 1:
The source field plate structure serves multiple functions simultaneously: it relaxes electric field concentration at the source end of the gate electrode, provides a self-aligning reference for positioning, and when combined with the insulating film, creates a multi-layer structure that can be formed using standard semiconductor fabrication processes. This multi-functionality reduces the need for additional separate structures.
Data Source
AI summary
A semiconductor device comprises a Group III nitride semiconductor lamination structure including a hetero-junction; an insulating layer formed on the Group III nitride semiconductor lamination structure, the insulating layer including a gate opening portion extending to the Group III nitride semiconductor lamination structure; a gate insulating film configured to cover a bottom portion and a side portion of the gate opening portion; a gate electrode formed on the gate insulating film in the gate opening portion; a source electrode and a drain electrode disposed in a spaced-apart relationship with the gate electrode to sandwich the gate electrode and electrically connected to the Group III nitride semiconductor lamination structure; and a conductive layer embedded in the insulating layer between the gate electrode and the drain electrode and insulated from the gate electrode by the gate insulating film, the conductive layer electrically connected to the source electrode.