Heterogeneous 3D Chip Stack Hybrid Bonding for Mobile Processors
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Solution Overview
Problem
As semiconductor manufacturing techniques advance, the cost of producing integrated circuits decreases with smaller node sizes, but below 20 nm, defects and quantum effects increase, leading to reduced yield and increased complexity in manufacturing, particularly for analog and radio-frequency circuits, which do not scale as effectively as digital circuits.
Innovation Solution
The integration of multiple dies manufactured on different wafers with varying node sizes, where high-density memory and analog circuits are produced on larger node sizes, while processing units and digital logic are on smaller node sizes, using a hybrid bonding technique to connect them, reducing power dissipation and increasing bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple dies with different node sizes are integrated using hybrid bonding, then bandwidth and power efficiency improve, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The system is divided into multiple dies with different node sizes (e.g., 7nm and 28nm) that are bonded together in a 3D stack. Each die handles specific workloads optimized for its node characteristics, enabling high-bandwidth communication between closely spaced dies while maintaining manufacturing feasibility through heterogeneous integration.
Solution Approach 2:
The patent transitions from 2D planar integration to 3D vertical stacking by bonding multiple dies together. This adds the vertical dimension to the system architecture, allowing high bandwidth through short vertical interconnects while distributing complexity across multiple layers rather than concentrating it in a single plane.
2Productivity
If smaller node sizes are used to reduce manufacturing cost per chip, then transistor density increases, but yield decreases due to defects and quantum effects below 20nm
Solution Approach 1:
Different regions of the system use different node sizes optimized for their specific requirements. High-performance digital logic that benefits from high transistor density uses smaller nodes (7nm), while analog/RF circuits and memory that are sensitive to defects use larger nodes (28nm). This local optimization allows each component to operate at its optimal node size, improving overall yield while maintaining high transistor density where needed.
Solution Approach 2:
The system uses a composite architecture combining multiple node sizes in a single package. This heterogeneous integration allows the system to leverage the high transistor density of smaller nodes for digital logic while using larger nodes for components requiring higher yield and reliability, effectively creating a composite solution that balances both competing requirements.
3Power
If all circuits are manufactured on the same wafer at the smallest node size, then performance is maximized, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The system segments the circuitry into different dies manufactured at different node sizes. Digital logic requiring high performance is fabricated at smaller nodes, while analog/RF circuits are fabricated at larger nodes using separate manufacturing processes. This segmentation allows each die to be optimized independently, reducing manufacturing complexity while maintaining overall system performance.
Solution Approach 2:
The hybrid bonding interface acts as an intermediary that connects dies from different manufacturing processes. This intermediary layer enables integration of circuits manufactured at different node sizes and by different foundries, allowing the system to achieve high performance without requiring all components to be manufactured using the most complex smallest-node process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the overall cost of the chip set by separating logic between expensive and cheap silicon, improving yield and reducing the complexity of the substrate, while maintaining performance by optimizing the placement of components based on their manufacturing feasibility.
Implementation Method 1
The first die may be mounted on a top surface of the second die utilizing a hybrid wafer bonding technique
Data Source
AI summary
An integrated circuit package and a system including the integrated circuit package as well as a process for assembling the integrated circuit package are provided. The integrated circuit package includes a first die manufactured on a first wafer utilizing a first node size, a second die manufactured on a second wafer utilizing a second node size, and a substrate coupled to the second die at a plurality of bump sites on a bottom surface of the second die. The first die may be mounted on a top surface of the second die utilizing a hybrid wafer bonding technique, micro bumps, or electrode-less plating.