Heterogeneous 3D Nanowire Integration for Mixed Signal Circuits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional CMOS device fabrication requires separate digital and analog chips with different substrate, voltage, frequency, and fabrication requirements, leading to increased chip real estate demands and complexity.
Innovation Solution
A method for forming Si or Ge-based and III-V-based vertically integrated nanowires on a single substrate, using trench formation, conformal layer deposition, and metal catalyst-assisted growth to integrate digital and analog circuits, enabling scalable and compatible integrated circuit fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate digital and analog chips are used with different substrates and fabrication requirements, then device performance requirements are met, but chip real estate demands and fabrication complexity increase
Solution Approach 1:
The patent merges digital and analog circuits onto a single substrate by integrating Si-based CMOS digital circuits and III-V based analog circuits in close proximity, eliminating the need for separate chips and reducing fabrication complexity while maintaining device performance
Solution Approach 2:
The patent applies local quality by using different materials (Si for digital, III-V for analog) in different regions of the same substrate, allowing each region to be optimized for its specific function while maintaining overall integration
2Reliability
If separate digital and analog chips are used, then specific voltage and frequency requirements are met, but chip real estate demands increase
Solution Approach 1:
The patent combines multiple chips with different voltage and frequency requirements into a single integrated device, reducing chip real estate while maintaining the ability to meet specific electrical requirements through localized circuit design
Solution Approach 2:
The patent transitions from planar 2D integration to 3D vertical integration by forming vertical nanowire channels, enabling higher transistor packing density and reduced chip area while maintaining functional separation between digital and analog regions
3Manufacturing precision
If silicon oxide is deposited conformally in trenches, then trench filling is achieved, but via hole formation requires additional processing steps
Solution Approach 1:
The patent performs preliminary action by forming via holes through the silicon oxide trench fill before completing the gate electrode formation, allowing subsequent processing steps to access underlying structures and maintain manufacturing precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the heterogeneous integration of Si or Ge-based and III-V-based channels for vertical FETs on a single substrate, allowing for both digital and analog logic integration on a single chip, with low voltage/power consumption and increased transistor packing density.
Implementation Method 1
growing the III-V or III-VxMy nanowires to a desired height by a metal catalyst vertical vapor liquid solid (VLS) growth
Implementation Method 2
forming a conformal silicon nitride (SiN), SiOxCyNz, or direct plasma nitride (DPN) layer
Data Source
AI summary
A method of forming Si or Ge-based and III-V based vertically integrated nanowires on a single substrate and the resulting device are provided. Embodiments include forming first trenches in a Si, Ge, III-V, or SixGe1-x substrate; forming a conformal SiN, SiOxCyNz layer over side and bottom surfaces of the first trenches; filling the first trenches with SiOx; forming a first mask over portions of the Si, Ge, III-V, or SixGe1-x substrate; removing exposed portions of the Si, Ge, III-V, or SixGe1-x substrate, forming second trenches; forming III-V, III-VxMy, or Si nanowires in the second trenches; removing the first mask and forming a second mask over the III-V, III-VxMy, or Si nanowires and intervening first trenches; removing the SiOx layer, forming third trenches; and removing the second mask.