Heterogeneous 3D Graphics Processor with Unified API Configuration

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Solution Overview

Problem

Traditional 3D graphics processors face challenges in combining the flexibility of programmable pipeline stages with the performance and low power consumption of fixed function pipeline stages, particularly in embedded systems where gate size and power constraints are limiting, and existing APIs do not support unified configuration of heterogeneous pipelines.

Innovation Solution

A graphic processor architecture that includes an arbiter unit to couple programmable and fixed function units in parallel, allowing programmable units to interact with and configure fixed function units as texture sampling units, and using a unified API for configuring both types of pipeline parts, enabling concurrent operation and efficient resource management.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a programmable pipeline stage is used, then flexibility is improved, but performance and gate size efficiency deteriorate

Engineering Contradiction:
ImproveflexibilityVSAvoidperformance
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The pipeline stage is segmented into multiple independent processing elements (PEs) that can be individually configured. Each PE can be programmed to perform specific functions, allowing the system to achieve both flexibility through programmability and performance through optimized parallel execution of segmented tasks.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The processing elements are designed with universal functionality, where each PE can be programmed to perform multiple different operations. This multi-functionality allows a single hardware structure to replace multiple specialized fixed-function units, achieving flexibility without proportionally increasing gate size, while maintaining high performance through parallel execution.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If a fixed function pipeline stage is used, then performance and gate size efficiency are improved, but flexibility deteriorates

Engineering Contradiction:
ImproveperformanceVSAvoidflexibility
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The fixed function processing elements incorporate dynamic reconfiguration capabilities through programmable control logic. This allows the hardware to switch between different operational modes and functions, providing flexibility while maintaining the performance characteristics of fixed-function designs when operating in optimized modes.

Inventive Principle:
Principle #15Dynamics

3Use of energy by stationary object

If a heterogeneous pipeline combining fixed function and programmable stages is used, then power consumption is reduced, but configuration complexity increases

Engineering Contradiction:
Improvepower consumptionVSAvoidconfiguration complexity
Core Design Contradiction:
Use of energy by stationary objectVSDevice complexity

Solution Approach 1:

The heterogeneous pipeline is presented through a unified homogeneous interface to software. All processing elements, whether fixed-function or programmable, are accessed through the same programming model and control mechanisms, eliminating the need for separate configuration paths and reducing overall system complexity despite the hardware heterogeneity.

Inventive Principle:
Principle #33Homogeneity

Data Source

PatentUS9619918B2Heterogenious 3D graphics processor and configuration method thereof
Publication Date: 2017.04.11 DIGITAL MEDIA PROFESSIONALS
  • US9619918B2 patent drawing
  • US9619918B2 patent drawing
  • US9619918B2 patent drawing

AI summary

To provide assemble programmable and fixed function pipe-line parts of a 3D graphics processor, combining flexibility of programmable pipeline for each stage and small gate size and speed of fixed function pipeline. The graphic processor couples a programmable unit with the texture sampling unit 16 and the fixed function unit 17 in parallel. The arbiter unit 18 and the texture sampling unit 16 are directly connected and the arbiter unit 18 and the fixed function unit 17 are also directly connected.