Heterojunction Semiconductor Corner Relief Region for Leakage Current Control
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Solution Overview
Problem
Conventional semiconductor devices experience decreased interruption characteristics due to leakage current concentration at the heterojunction interface, particularly at the level difference generated at the end of the heterojunction interface when arranged in parallel, leading to reduced performance under reverse bias conditions.
Innovation Solution
A current-concentration relief region is formed at the corner of the heterojunction interface by using P−-type polycrystalline silicon regions with lower impurity density, which reduces current concentration and enhances the energy barrier, thereby improving interruption characteristics and preventing hot spots during operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple semiconductor devices are arranged in parallel, then device density and integration are improved, but level differences at heterojunction interfaces generate leakage current concentration and reduce interruption characteristics
Solution Approach 1:
The patent applies local quality by forming a P-type semiconductor region specifically at the corner portion of the heterojunction interface where level differences occur. This localized modification creates a potential barrier only at the problematic corner regions, preventing leakage current concentration without affecting the overall device performance or requiring changes to the entire device structure.
Solution Approach 2:
The patent implements preliminary anti-action by proactively forming P-type semiconductor regions at corner portions before leakage current problems manifest. These regions create potential barriers in advance that prevent leakage current concentration at heterojunction interface level differences, thereby maintaining good interruption characteristics even when multiple devices are arranged in parallel.
2Ease of manufacture
If heterojunction interface is formed with polycrystalline silicon region, then device fabrication is simplified, but level differences at interface corners cause leakage current and reduced interruption performance
Solution Approach 1:
The patent maintains the simple polycrystalline silicon heterojunction structure for ease of manufacture, but locally modifies corner portions by forming P-type semiconductor regions. This selective modification addresses the leakage current issue at specific problem areas without complicating the overall fabrication process or requiring complete restructuring of the heterojunction interface.
Solution Approach 2:
The P-type semiconductor region acts as an intermediary element at the corner portions of the heterojunction interface. It mediates between the N-type drift region and the polycrystalline silicon region, creating a potential barrier that prevents leakage current while maintaining the simplicity of the original polycrystalline silicon-based heterojunction structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively decreases leakage current at the convex corners, improving interruption performance, preventing hot spots, and enhancing long-term reliability and breakdown tolerance by ensuring uniform current distribution across the semiconductor chip.
Implementation Method 1
a P-type semiconductor region is formed at a corner portion of a heterojunction interface between an N-type semiconductor region and a polycrystalline silicon region. The P-type semiconductor region forms a potential barrier together with the N-type semiconductor region in a direction perpendicular to a surface of the N-type semiconductor region
Data Source
AI summary
A hetero semiconductor corner region, which is a current-concentration relief region that keeps a reverse bias current from concentrating on the convex corner, is arranged in a hetero semiconductor region. Thereby, a current concentration on the convex corner can be prevented. As a result, an interrupting performance can be improved at the time of interruption, and at the same time, the generation of the hot spot where in a specific portion is prevented at the time of conduction to suppress deterioration in a specific portion, thereby ensuring a long-term reliability. Further, when the semiconductor chip is used in an L load circuit or the like, for example, at the time of conduction or during a transient response time to the interrupted state, in an index such as a short resistant load amount and an avalanche resistant amount, which are indexes of a breakdown tolerance when overcurrent or overvoltage occurs, the current concentration on a specific portion can be prevented, and thus, these breakdown tolerances can also be improved.