Semiconductor Heterojunction Facet Engineering for Photocurrent
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Solution Overview
Problem
Current semiconductor technologies face challenges in harnessing the unique properties of faceted semiconductors for enhanced electrical and optical applications, particularly in miniaturized transistors and photodetectors, due to the lack of effective methods to exploit facet-dependent effects.
Innovation Solution
A semiconductor heterojunction is created by combining a bottom semiconductor with a top semiconductor, where the upper surface of the bottom semiconductor and the lower surface of the top semiconductor have specific facets, allowing for controlled facet interactions and electrical contact through an electrode substrate, enabling observation and application of facet effects in electronic and optical devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional semiconductor structures are used, then manufacturing simplicity is maintained, but facet-dependent electrical and optical properties cannot be exploited
Solution Approach 1:
The semiconductor structure is segmented into multiple crystals with different facets, where each crystal contributes specific facet-dependent properties. The heterojunction is divided into first and second semiconductors with controlled facet orientations, allowing independent optimization of electrical and optical characteristics for each segment.
Solution Approach 2:
Different facets of the semiconductor crystals are positioned at specific locations to create local quality variations. The first and second facets are strategically oriented to exploit anisotropic electrical conductivity and optical absorption in different regions, enabling spatially-resolved functional optimization within the heterojunction.
2Length of moving object
If nanomaterials are used for miniaturization, then device size is reduced, but control over facet effects is lost
Solution Approach 1:
The facet orientations of the semiconductor crystals are predetermined and controlled during the crystal growth process before device assembly. By pre-forming crystals with specific facet orientations and then assembling them into the heterojunction, the patent achieves both miniaturization and precise facet control, as the critical facet geometry is established in advance rather than requiring post-assembly alignment.
3Reliability
If facet-controlled semiconductors are implemented, then electrical conductivity and photocurrent response are improved, but device fabrication complexity increases
Solution Approach 1:
The patent introduces an intermediary approach where pre-fabricated semiconductor crystals with controlled facets serve as building blocks. These intermediary components are manufactured separately with precise facet control, then assembled into the final heterojunction device, thereby decoupling the complex facet-control process from the overall device fabrication and enabling modular manufacturing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The semiconductor heterojunction demonstrates facet-dependent electrical conductivity and photocatalytic properties, suitable for field effect transistors and photodetectors, with specific facet combinations showing improved conductivity and photocurrent responses, facilitating the development of advanced electronic and optical devices.
Implementation Method 1
there are references proving that various faceted semiconductors, including crystals such as Ag2O, TiO2 or PbS, have conductive, photocatalytic, or optical properties related to the facet effect
Implementation Method 2
various faceted semiconductors, including crystals such as Ag2O, TiO2 or PbS, have conductive, photocatalytic, or optical properties related to the facet effect
Data Source
AI summary
The present disclosure provides a semiconductor heterojunction. The semiconductor heterojunction includes a bottom semiconductor, a top semiconductor and an electrode substrate. An upper surface of the bottom semiconductor includes a first facet. A lower surface of the top semiconductor includes a second facet, and the lower surface of the top semiconductor is contacted with the upper surface of the bottom semiconductor. The electrode substrate is disposed below the bottom semiconductor.


