Hexagonal GAA Memory Cells With Angled Digit-Line Shielding
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Solution Overview
Problem
Current memory devices face challenges in enhancing performance and reducing leakage power while maintaining a compact die size, particularly in achieving efficient integration of memory cells and control logic in semiconductor ICs.
Innovation Solution
The development of a memory device with an array of hexagonal memory cells, each featuring a gate-all-around (GAA) transistor coupled to a capacitor, implemented in a circuit over array (CoA) architecture. This design includes angled digit lines and access lines, along with metal shield lines, to optimize interconnects and reduce die size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional memory cell designs are used, then manufacturing and integration are simpler, but on-state current capability and performance are limited
Solution Approach 1:
The patent transitions from planar 2D transistor structures to three-dimensional gate-all-around (GAA) nanowire structures. The gate completely surrounds the nanowire channel in all directions (top, bottom, sides), creating a 3D configuration that provides superior electrostatic control and significantly enhanced on-state current capability compared to conventional planar transistors.
Solution Approach 2:
The patent employs composite material structures including semiconductor nanowires (such as SiGe or III-V materials like InGaAs) combined with gate dielectric materials and metal gates. These composite material systems enable optimized carrier mobility, threshold voltage control, and current drive while maintaining the benefits of the GAA architecture.
2Quantity of substance
If more memory cells are integrated to increase capacity, then storage density improves, but leakage power increases
Solution Approach 1:
The GAA nanowire structure enables vertical stacking of multiple nanowires within a single memory cell footprint, transitioning from lateral scaling to vertical integration. This three-dimensional arrangement increases memory cell density while the complete gate surround provides excellent off-state control, suppressing leakage currents even as density increases.
Solution Approach 2:
The patent applies different material compositions and doping profiles to specific regions of the nanowire structure (e.g., undoped channel regions for low leakage, doped source/drain regions for high current drive). This localized optimization allows high density integration while maintaining low leakage power through precise spatial control of electrical properties.
3Area of stationary object
If die size is reduced to improve integration, then device compactness improves, but manufacturing precision requirements increase
Solution Approach 1:
By moving to vertical nanowire structures growing perpendicular to the substrate, the patent achieves compact lateral footprints. The self-aligned nature of vertical nanowire formation and the use of epitaxial growth techniques enable precise control of nanowire position and dimensions, facilitating miniaturization without proportionally increasing manufacturing difficulty.
Solution Approach 2:
The patent employs preliminary patterning steps and sacrificial layer techniques to pre-establish precise nanowire locations before final device formation. Seed layers and template structures are formed in advance with high precision, guiding subsequent nanowire growth to achieve the required manufacturing precision for compact die sizes.
4Ease of operation
If gate-all-around transistors are implemented, then on-state current and threshold voltage control improve, but device complexity and fabrication difficulty increase
Solution Approach 1:
The patent enables continuous adjustment of threshold voltage by varying nanowire material composition (e.g., InGaAs with different In content), doping concentrations, and gate dielectric properties. The complete gate surround provides uniform electrostatic control from all directions, allowing precise threshold voltage tuning through material parameter optimization rather than complex geometric adjustments.
Data Source
AI summary
A variety of applications can include a memory device having an array of memory cells arranged as hexagonal cells, with each of the memory cells having a gate-all-around (GAA) transistor coupled to a capacitor. Digit lines to the memory cells can be arranged angled relative to the set of access lines at an angle different from ninety degrees. Digit shield lines can be structured between adjacent digit lines. The memory device can be arranged in a wafer-to-wafer interconnect architecture with the array on an array wafer connected to and below a control circuitry wafer in a circuit over array architecture.