Hierarchical Bit Line Memory Array with Selector Regions
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Solution Overview
Problem
Existing memory cell arrays with hierarchical bit line structures face challenges in optimizing bit line resistance and signal margin, particularly in dividing memory cells into efficient sub-groups and coupling them with selector transistors for high-speed operation.
Innovation Solution
The memory array design includes a plurality of word lines with selector regions that divide memory cells into sub-groups, with main bit lines extending orthogonally and coupled to selector transistors, reducing bit line resistance and improving signal margins through staggered and symmetric selector configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory cells are divided into sub-groups with selector regions, then signal margin is improved, but device complexity increases
Solution Approach 1:
The memory cell array is divided into multiple sub-groups along the bit line direction, with each sub-group having its own selector region. This segmentation allows for better signal margin by isolating different memory cell groups, while the systematic arrangement keeps the added complexity manageable.
Solution Approach 2:
Selector regions are introduced as intermediary components between the bit lines and memory cell sub-groups. These selector regions act as mediators that improve signal integrity by providing controlled access to each sub-group, thereby enhancing signal margin without requiring complete redesign of the memory architecture.
2Manufacturing precision
If selector regions are disposed at distal ends of SBL, then manufacturing precision is improved, but bit line resistance increases
Solution Approach 1:
Selector regions are strategically positioned at distal ends of sub-bit lines where manufacturing precision can be maximized, while the overall bit line structure is designed with appropriate width and spacing to compensate for the increased resistance. This localized optimization allows manufacturing precision to be improved without completely sacrificing electrical performance.
Data Source
AI summary
A memory array includes a plurality of word lines extending along a first direction; a plurality of memory cells coupled to a first sub-bit line (SBL) extending along a second direction that is substantially orthogonal to the first direction; a first selector region disposed substantially in the middle of the first SBL thereby dividing the plurality of memory cells into two sub-groups, wherein the first selector region comprises at least one selector transistor that is coupled to the first SBL; and a main bit line (MBL) extending along the second direction and coupled to the selector transistor.