Hierarchical Bitline Structure for DRAM Signal Routing
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Solution Overview
Problem
As DRAM feature sizes shrink, routing shorter bitlines to sense amplifiers becomes challenging due to the increasing ratio of bitline parasitic capacitance to cell capacitance, requiring innovative solutions to maintain signal integrity and reduce the number of sense amplifiers needed.
Innovation Solution
A hierarchical bitline structure is implemented, with local bitlines separated into sections and connected to global bitlines via bitline isolation switches, allowing for shorter local bitlines with higher per-length capacitance and longer global bitlines with lower per-length capacitance to route signals to remote sense amplifiers, reducing the need for numerous sense amplifiers and enabling greater distance between them and the memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If bitlines are shortened to maintain low parasitic capacitance ratio, then bitline length is reduced, but routing to sense amplifiers becomes more challenging
Solution Approach 1:
The bitline structure is segmented into local bitlines (shorter segments) and global bitlines (longer segments), allowing each segment to serve its specific function optimally while maintaining overall system performance
Solution Approach 2:
The patent introduces a two-dimensional bitline hierarchy with local and global bitlines operating at different levels, enabling signal routing to sense amplifiers through multiple pathways and dimensions rather than relying on single long bitlines
2Object-affected harmful factors
If local bitlines are made shorter with higher per-length capacitance, then parasitic capacitance is reduced, but signal routing distance is limited
Solution Approach 1:
The bitline is divided into local segments with higher capacitance density for short-distance cell connections and global segments with lower capacitance density for long-distance signal routing to sense amplifiers
Solution Approach 2:
Different segments of the bitline structure are assigned different capacitance characteristics - local bitlines have higher per-length capacitance optimized for short distances, while global bitlines have lower per-length capacitance optimized for long distances
3Quantity of substance
If sense amplifiers are placed farther from memory cells, then device density is improved, but signal integrity may be compromised
Solution Approach 1:
The hierarchical bitline structure creates multiple routing dimensions and pathways, allowing sense amplifiers to be positioned at optimal distances while maintaining signal integrity through the structured local-global bitline connection system
Data Source
AI summary
A dynamic random access memory (DRAM) device has a hierarchical bitline structure with local bitlines and global bitlines formed on different metal layers. The local bitlines are separated into a plurality of local bitline sections, and bitline isolation switches are configured to connect or disconnect the local bitline sections to or from the global bitlines. As a result, the local bitlines with higher per-length capacitance can be made shorter, since the global bitline with lower per-length capacitance is used to route the signal from the cell capacitances of the memory cells to the remote sense amplifiers.