Hierarchical Circuit Partitioning for Simulation Speed
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Solution Overview
Problem
Existing circuit simulators face challenges in achieving fast and accurate simulations of large integrated circuits without significantly increasing memory consumption, as they either require extensive processing time or sacrifice accuracy for efficiency.
Innovation Solution
The method involves hierarchical partitioning of electrical circuits into sub-circuits, ranking them based on parent-child relationships, and duplicating sub-circuits connected to voltage sources to optimize simulation by treating instances as black boxes and reducing memory usage through abstract views and directed graphs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the entire circuit is simulated as a single matrix, then simulation accuracy is maintained, but processing time increases significantly
Solution Approach 1:
The patent divides the circuit into multiple sub-circuits and partitions them into smaller groups, transforming the single large matrix into multiple smaller matrices. This segmentation allows the simulator to process smaller, more manageable matrices while maintaining the overall circuit behavior through hierarchical organization, thereby reducing processing time without sacrificing accuracy.
Solution Approach 2:
The patent implements a hierarchical partitioning structure where sub-circuits are nested within parent sub-circuits, creating multiple levels of organization. This nested structure allows the simulator to solve smaller matrices at different hierarchical levels, with the results being combined to produce the overall circuit simulation, thus reducing processing time while maintaining accuracy.
2Productivity
If the circuit is flattened into small groups for partitioning, then processing speed improves, but memory consumption increases significantly
Solution Approach 1:
The patent applies different partitioning strategies to different parts of the circuit based on their specific characteristics. By analyzing the circuit hierarchy and applying partitioning only where necessary, the method reduces memory consumption compared to uniform flattening, while still achieving improved processing speed through the solution of smaller matrices.
Solution Approach 2:
The patent performs preliminary analysis of the circuit hierarchy to identify sub-circuits that can be partitioned independently. This preliminary action allows the simulator to organize the circuit into manageable partitions before simulation, reducing memory requirements while maintaining processing speed benefits.
3Productivity
If timing simulators use simplified device models and equation formulation, then processing efficiency improves, but simulation accuracy decreases
Solution Approach 1:
The patent segments the circuit into sub-circuits and uses accurate device models for each segment while employing efficient equation formulation techniques. This allows the simulator to maintain high accuracy through precise modeling of individual sub-circuits while improving processing efficiency through the modular structure that enables parallel processing and reduced computational complexity.
Data Source
AI summary
Some embodiments provide a method of simulating an electrical circuit that receives a circuit description that has a set of sub-circuits. The method defines several partitions for several sub-circuits. The method then simulates the circuit using the partitioned sub-circuits. In some embodiments, the method ranks the sub-circuits prior to partitioning based on a parent-child relationship that shows how a sub-circuit is instantiated by other sub-circuits. These embodiments partition child sub-circuits first. Some embodiments provide a method of partitioning an electrical circuit that has a set of sub-circuits. For a particular sub-circuit that is instantiated from other sub-circuits, the method duplicates the particular sub-circuit into a first copy and a second copy when one port of the particular sub-circuit is connected to a voltage source in at least one instance and the same port is not connected to a voltage source in at least another instance.