Hierarchical Verification for Data Transformation Hardware

The patent divides the complex data transformation component into multiple hierarchical levels of sub-components. Each sub-component is verified separately at its own level, breaking down the overwhelming verification task into manageable segments. This hierarchical segmentation allows formal verification to be applied to smaller, more tractable units rather than attempting to verify the entire complex system at once.

The patent introduces an intermediary verification layer that sits between the detailed hardware design and the formal verification process. This intermediary layer abstracts the complex data transformations into intermediate representations that are more amenable to formal verification, acting as a mediator that translates the complex system into a form that verification tools can handle efficiently.

The patent segments the verification coverage requirement into hierarchical levels, where each level handles a specific subset of transformation cases. Instead of managing a single large set of test signals for all cases, the verification process is divided into multiple levels, each with its own manageable set of test signals focused on specific transformation scenarios.

The patent adds a hierarchical dimension to the verification process, organizing test signals and transformation cases across multiple levels rather than in a single flat structure. This dimensional organization allows test signals to be grouped and managed at different hierarchical levels, reducing the complexity of managing all test signals simultaneously while maintaining comprehensive coverage.