Hierarchical Memory Indexing for Ordered Multicore 3-D Rendering
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Solution Overview
Problem
Implementing rendering tasks in parallel on a multicore GPU while maintaining the order of primitives as provided by the application driver and managing memory efficiently to facilitate the rendering of complex scenes.
Innovation Solution
A multicore graphics rendering system with a hierarchical memory management system that uses allocation lists and virtualised memory spaces to manage memory allocation and ordering of rendering tasks, ensuring efficient parallel processing of geometry and fragment processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If rendering tasks are processed in parallel on multicore GPU, then rendering speed is improved, but memory management complexity increases
Solution Approach 1:
The patent segments the virtual memory space into multiple virtual address spaces, with each core having its own dedicated virtual address space. This segmentation isolates memory management for each core, simplifying the overall system by preventing memory conflicts between cores while still enabling parallel processing. The allocation list is also segmented to track memory allocations per core independently.
Solution Approach 2:
The patent introduces an allocation list as an intermediary data structure that mediates between the virtual memory space and physical memory allocations. This allocation list tracks which virtual address ranges are allocated to which cores and maintains ordering information, serving as a mediator that simplifies memory management operations without requiring complex inter-core coordination protocols.
2Productivity
If memory is allocated for parallel rendering tasks, then rendering capability is improved, but memory usage increases
Solution Approach 1:
The patent implements dynamic memory allocation where the virtual address space and allocation list are adjusted based on actual rendering needs. Memory is allocated to cores on-demand rather than statically pre-allocated, and the allocation list dynamically tracks and releases memory as rendering tasks complete. This dynamic approach allows the system to handle complex scenes when needed while releasing memory when not required, optimizing the balance between capability and usage.
Solution Approach 2:
The patent enables memory recovery by tracking allocated virtual address ranges in the allocation list and identifying when these ranges are no longer needed. Once rendering tasks using specific memory regions complete, the system can discard those allocations and recover the physical memory for reuse by other cores or tasks, thus managing memory quantity efficiently while maintaining rendering capability.
3Manufacturing precision
If primitive ordering is maintained in parallel processing, then rendering accuracy is improved, but processing overhead increases
Solution Approach 1:
The patent applies preliminary action by pre-assigning specific virtual address ranges to each core in the allocation list before parallel processing begins. Each core's memory allocation is pre-configured with ordering information, so that when rendering tasks are distributed, the ordering requirements are already embedded in the memory allocation structure. This eliminates the need for complex runtime coordination to maintain primitive ordering, reducing processing overhead while preserving rendering accuracy.
Data Source
AI summary
A multicore graphics rendering system includes a plurality of cores configured to implement tile-based rendering of a stream of primitives. The graphics rendering system uses at least one virtualised memory space. A hierarchical index is provided, to index the physical memory portions associated with virtual memory portions in the at least one virtualised memory space. The portions of memory allocated for the hierarchical index are recorded in an MMU (memory management unit) list (MLIST). The MLIST comprises a plurality of entries, each entry being associated with a respective portion of the hierarchical index, wherein each entry includes an indication of the portion of virtual memory that is indexed by that portion of the hierarchical index. The MLIST is used to identify, and free, portions of memory associated with indexing virtual memory that has been fully consumed in a partial render.