Hierarchical NoC Multi-Instancing for Scalable Backend Closure
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Solution Overview
Problem
Existing NoC designs are limited to flat topologies, preventing a bottom-up approach that could reduce complexity and overheads in chip backend processes, and lack scalability and resource utilization due to inflexible interconnect architectures.
Innovation Solution
Construct NoCs using a hierarchical topology composed of sub-NoCs and leaf components, allowing multi-instancing and incorporating chipset awareness to create adaptable communication infrastructures through algorithmic elaboration and connectivity definitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If flat topology is used for NoC design, then implementation is straightforward, but scalability and resource utilization are limited
Solution Approach 1:
The patent divides the NoC into hierarchical segments: root nodes representing sub-NoCs and leaf nodes representing components or sub-NoCs. This segmentation allows the system to scale by adding more leaf nodes without fundamentally changing the overall topology structure, thereby improving scalability while maintaining manageable complexity through modular organization.
Solution Approach 2:
The patent introduces a hierarchical dimension to the traditional flat NoC topology. By organizing nodes into multiple levels (root nodes and leaf nodes) with defined connectivity rules, the system adds a vertical dimension to the horizontal network structure, enabling scalable expansion while preserving routing simplicity through algorithmic elaboration.
2Productivity
If multi-instancing is implemented, then resource utilization improves, but design and verification complexity increases
Solution Approach 1:
The patent enables multi-instancing by allowing leaf nodes to represent multiple instances of the same sub-NoC or component. Instead of designing each instance separately, the same design can be instantiated multiple times in the hierarchical topology, improving resource utilization while reducing design complexity through reuse. The algorithmic elaboration process automatically handles the multiplication and connectivity of these instances.
3Ease of manufacture
If bottom-up approach is adopted, then complexity in backend processes reduces, but traditional flat topology limitations persist
Solution Approach 1:
The patent applies bottom-up design by allowing sub-NoCs to be designed, validated, and elaborated independently before being instantiated as root nodes in the hierarchical topology. This preliminary action on smaller units reduces backend process complexity because each sub-NoC can be optimized and verified separately. The hierarchical structure then combines these pre-elaborated units, maintaining topology flexibility through the algorithmic generation of interconnections.
Data Source
AI summary
Apparatus and methods for constructing Network on Chips (NoCs) by algorithmically elaborating one or more of Network on Chips (NoCs) through a hierarchical topology composed of instantiations of sub-NoCs and leaf components, and one or more connectivity definitions. Designing NoCs using one or more instantiations of sub-NoCs reduces overheads during chip backend processes, such as for timing closure.