High Aspect Ratio Etching for 3D NAND Memory Stacks
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Solution Overview
Problem
Manufacturing 3D memory devices with vertical gate (VG) 3D NAND architecture faces challenges due to the increased number of layers, which can lead to mechanical issues such as bending and collapsing of stacks, especially with narrower widths that are difficult to reliably produce and support more layers of memory cells.
Innovation Solution
The method involves forming a plurality of semiconductor layers alternating with insulating layers on an integrated circuit substrate, etching to define stacks of active strips with an initial width greater than twice the target width, then dividing these stacks into narrower widths to form memory cells with conductive lines that act as word lines, allowing for more reliable manufacturing and higher aspect ratios, thus supporting more layers without mechanical issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If stacks are made with narrower width (1F) to increase memory cell density, then memory cell density is improved, but mechanical stability deteriorates leading to bending and collapsing
Solution Approach 1:
The patent applies segmentation by dividing the manufacturing process into stages: first forming wider stacks (greater than 2F width) that provide mechanical stability, then subsequently dividing these stacks into narrower segments (1F width) that achieve high density. This is accomplished through multiple etching steps that split the initial wide stacks into finer structures, allowing both stability during fabrication and final high density to be achieved.
Solution Approach 2:
The patent employs preliminary action by first forming the stacks with a larger width (greater than 2F) before the final division step. This preliminary wider structure provides the mechanical stability needed during subsequent processing steps, and only after this stable structure is established is it divided into the final narrow 1F stacks. This preliminary wider configuration prevents bending and collapsing during manufacturing.
2Stability of the object's composition
If stacks are made with wider width (greater than 2F) to improve mechanical stability, then mechanical stability is improved, but manufacturing precision deteriorates as it becomes difficult to produce narrower widths
Solution Approach 1:
The patent segments the width control process into multiple steps: first establishing a wide stack structure (greater than 2F) that is easy to manufacture with good mechanical stability, then using subsequent division steps to achieve the precise narrow width (1F). This multi-stage segmentation approach avoids the difficulty of directly manufacturing narrow stacks while achieving both stability and precision.
Solution Approach 2:
The patent performs preliminary formation of wide stacks (greater than 2F width) that are straightforward to manufacture with high mechanical stability. Only after this preliminary wide structure is successfully formed does the process proceed to divide it into the final narrow stacks. This preliminary action simplifies the manufacturing process by avoiding direct fabrication of narrow structures.
3Quantity of substance
If more layers of memory cells are added to increase storage capacity, then storage capacity is improved, but device complexity increases leading to more mechanical issues
Solution Approach 1:
The patent applies preliminary action by first establishing wide stacks (greater than 2F width) that provide enhanced mechanical stability before adding multiple layers of memory cells. This preliminary wide structure serves as a robust foundation that can support higher layer counts without bending or collapsing, thereby enabling increased storage capacity while managing the complexity of multi-layer structures.
Data Source
AI summary
A plurality of semiconductor layers is etched to define a first plurality of stacks of active strips between a first plurality of trenches. A first memory layer is formed on side surfaces of active strips in the first plurality of trenches, and a first layer of conductive material is formed over the first memory layer. The first plurality of stacks is etched to define a second plurality of stacks of active strips between a second plurality of trenches of the plurality of semiconductor layers. A second memory layer is formed on side surfaces of active strips in the second plurality of trenches, and a second layer of conductive material is formed over the second memory layer. Channel regions of memory cells in the memory device are formed in active strips of the plurality of semiconductor layers in the second plurality of stacks.