High Aspect Ratio Via Structures in Low-k Dielectric
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Solution Overview
Problem
Conventional methods for manufacturing semiconductor devices with high aspect ratio via holes are limited by the properties of negative-type photosensitive BCB, resulting in restricted via hole size and residual material issues, which hinder further miniaturization and lead to manufacturing and electrical problems.
Innovation Solution
A method utilizing a positive-type photoresist layer to form via structures with high aspect ratios, followed by sealing with low-k dielectric material, allowing for aspect ratios between 0.167 and 2, and utilizing dry etching to remove redundant material, enabling smaller via hole diameters and preventing subsequent process issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If negative-type photosensitive BCB is used to form via holes, then the dielectric material layer can be patterned, but the via hole size is limited and the aspect ratio is restricted to less than 0.167
Solution Approach 1:
The patent inverts the conventional approach by using positive-type photoresist instead of negative-type photosensitive BCB. This inversion allows the photoresist to be removed after electroplating, creating via holes with much higher aspect ratios (greater than 0.167) while maintaining precise control over via hole dimensions through the photoresist pattern layer.
Solution Approach 2:
The patent segments the dielectric material layer formation into distinct steps: first forming the photoresist pattern layer with the via hole pattern, then electroplating metallic material through the photoresist, and finally removing the photoresist. This segmentation allows each step to be optimized independently, achieving both precise via hole sizing and high aspect ratios.
2Volume of moving object
If negative-type photosensitive BCB is used to form small-sized via holes, then miniaturization is attempted, but residual BCB remains in the via holes causing manufacturing and electrical problems
Solution Approach 1:
The patent extracts the photoresist material layer after it has served its purpose as a pattern definition and electroplating mask. By removing the positive-type photoresist after electroplating, the via holes are completely cleared of residual materials, eliminating the reliability issues associated with trapped BCB while maintaining small via hole volumes for device miniaturization.
3Volume of stationary object
If the via hole diameter is reduced to achieve smaller capacitor size, then the capacitor volume decreases, but the aspect ratio requirement becomes more stringent and is limited by the photoresist properties
Solution Approach 1:
The patent changes the material parameter from negative-type photosensitive BCB to positive-type photoresist, which fundamentally alters the achievable aspect ratio parameter. This material parameter change enables via holes with aspect ratios greater than 0.167, allowing smaller via hole diameters and thus smaller capacitor volumes without sacrificing manufacturability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the creation of semiconductor devices with high aspect ratio via structures that are not limited by the properties of photosensitive materials, allowing for smaller feature sizes and improved manufacturing and electrical performance by using non-photosensitive low-k dielectric materials and dry etching to prevent residual material issues.
Implementation Method 1
patterning the positive-type photoresist layer for defining at least one through hole which exposes a part of the patterned metallic-trace layer
Implementation Method 2
electroplating a metallic material in the through hole so as to form a metallic pillar
Implementation Method 3
utilizing dry etching to remove redundant material
Data Source
AI summary
A method for manufacturing a device having a via structure includes the following steps. A seed metallic layer is formed on a substrate. A patterned metallic-trace layer is formed on the seed metallic layer. A positive-type photoresist layer is formed on the patterned metallic-trace layer and seed metallic layer. The photoresist layer is patterned for defining a through hole which exposes a part of the patterned metallic-trace layer, wherein the through hole has a high aspect ratio. A metallic material is electroplated in the through hole so as to form a metallic pillar. The photoresist layer is removed. A part of the seed metallic layer is etched, whereby traces of the patterned metallic-trace layer are electrically isolated from each other. A dielectric material layer is formed on the substrate for sealing the patterned metallic-trace layer and a part of the metallic pillar and exposing a top surface of the metallic pillar.