High-frequency component with exposed metal pins
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Solution Overview
Problem
High-frequency components with inductors built into multilayer substrates face issues of increased resistance and variability due to stacking deviations, limiting size reduction and performance in compact electronic devices.
Innovation Solution
A high-frequency component design featuring metal pins exposed from both surfaces of an insulating layer, connected to electronic components with low-resistance electrodes, reducing parasitic inductance and allowing for compact, high-Q inductor configurations with minimal variability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If via conductors or through hole conductors are formed by filling holes with conductive paste, then the inductor can be built into the multilayer substrate, but the connection areas between adjacent conductors decrease due to stacking deviations, causing increased resistance and variations in resistance values
Solution Approach 1:
The patent extracts the problematic via conductors formed by filling holes with conductive paste and replaces them with metal pins inserted into through holes. This extraction eliminates the stacking deviation issue that causes connection area reduction and resistance variations, while maintaining the capability to build inductors into multilayer substrates.
Solution Approach 2:
The patent changes the formation method parameter from 'filling holes with conductive paste' to 'inserting metal pins'. This parameter change transforms the conductor formation process, eliminating the sensitivity to stacking deviations and achieving stable resistance values even when connection areas vary.
2Productivity
If the inductor is built into the multilayer substrate using conventional methods, then the high-frequency circuit functionality is achieved, but the size reduction of the high-frequency component is limited
Solution Approach 1:
The patent utilizes the vertical dimension by inserting metal pins through the thickness of the multilayer substrate. This dimensional approach allows compact routing of high-frequency circuits, reducing the planar footprint and enabling overall size reduction while maintaining full functionality.
Solution Approach 2:
The patent embeds metal pins within the multilayer substrate structure, nesting the conductor elements inside the insulating layers. This nesting approach consolidates the inductor construction within the substrate volume, reducing the external dimensions of the high-frequency component.
3Device complexity
If via conductors are formed by filling holes with conductive paste, then the inductor construction is simplified, but the relative resistance is high and variations between resistance values are large
Solution Approach 1:
The patent extracts the conductive paste filling process and replaces it with metal pin insertion. This extraction eliminates the inherent variability and high resistance characteristics of paste-filled conductors, achieving consistent low resistance values across all connections.
Solution Approach 2:
The patent uses identical metal pins for all conductor connections, ensuring uniform material properties and dimensions. This copying approach guarantees consistent resistance values across all inductor windings, eliminating variations that occur with paste-filled conductors.
Data Source
AI summary
A high-frequency component includes a resin layer and a high-frequency circuit provided in and on the resin layer and includes an inductor and an electronic component. The electronic component is arranged on an upper surface of the resin layer. The inductor includes first and second metal pins provided such that upper end surfaces thereof are exposed from the upper surface of the resin layer and lower end surfaces thereof are exposed from a lower surface of the resin layer. The electronic component has a first outer electrode provided at a position superposed with the upper end surface of the first metal pin in plan view and is connected to the first metal pin, and a second outer electrode provided at a position superposed with the upper end surface of the second metal pin in plan view and is connected to the second metal pin.