High-Frequency Module Vertical Stacking Reduces Parasitic Capacitance
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Solution Overview
Problem
High-frequency modules with multiple demultiplexer chips face challenges in enhancing the sensitivity characteristic of communication systems, leading to suboptimal performance in 3G communication systems.
Innovation Solution
A high-frequency module design featuring a rectangular mounting substrate with strategically arranged demultiplexer chips, antenna and signal terminals, and wiring lines, which includes transmission and reception filter units and ground terminals, optimized to reduce parasitic capacitance and maintain impedance characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple demultiplexer chips are installed in a high-frequency module, then the functionality for 3G communication systems is improved, but the sensitivity characteristic deteriorates
Solution Approach 1:
The patent transitions from a conventional planar arrangement to a three-dimensional stacked configuration where demultiplexer chips are vertically arranged on the mounting substrate. This vertical stacking in the third dimension reduces the horizontal footprint and minimizes parasitic capacitance between adjacent chips, thereby maintaining sensitivity characteristics while supporting multiple 3G communication functions.
Solution Approach 2:
The patent implements a nested structure where multiple demultiplexer chips are stacked vertically, with each chip containing transmission and reception filter units. The chips are arranged in a compact vertical configuration, with lower chips serving as support for upper chips, creating a space-efficient nested arrangement that reduces parasitic effects while maintaining full functionality.
2Area of stationary object
If multiple demultiplexer chips are closely arranged, then the device size is reduced, but parasitic capacitance increases
Solution Approach 1:
The patent resolves the contradiction between compact size and parasitic capacitance by moving the arrangement from a two-dimensional planar layout to a three-dimensional vertical stack. This dimensional transition allows chips to be closely positioned in space (reducing module size) while the vertical separation and optimized wiring paths minimize parasitic capacitance between adjacent chips.
Solution Approach 2:
The patent introduces ground terminals and ground wiring lines as intermediary elements between adjacent demultiplexer chips. These ground structures act as shielding barriers that electrically isolate adjacent chips, reducing parasitic capacitance coupling while allowing the chips to be arranged in a compact vertical configuration.
3Reliability
If complex wiring lines are used to connect terminals, then the impedance characteristic is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent incorporates ground terminals and ground wiring lines into the mounting substrate design before chip mounting. These preliminary ground structures are pre-configured to provide impedance control and electromagnetic shielding, simplifying the overall manufacturing process while ensuring optimal impedance characteristics for the high-frequency signals.
Solution Approach 2:
The patent optimizes the wiring line configuration by changing the electrical parameters of the mounting substrate, including dielectric constant and loss tangent, to achieve controlled impedance characteristics. The wiring lines are designed with specific width, spacing, and layer configurations that maintain consistent impedance throughout the signal path, reducing the need for complex adjustments during manufacturing.
Data Source
AI summary
In a high-frequency module, an arrangement order of antenna terminals, transmission-side signal terminals, and reception-side signal terminals in a second direction corresponds to an arrangement order of antenna terminal electrodes, transmission-side terminal electrodes, and reception-side terminal electrodes in the second direction.