High-k Charge Trapping Layer for Non-Volatile Memory Cells
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Solution Overview
Problem
Conventional non-volatile memory cells using silicon nitride for charge storage face limitations in trap density and data retention, particularly with thinner layers, which can lead to reduced performance and increased thickness, compromising capacitive coupling and cell efficiency.
Innovation Solution
The use of a high-k charge storage region with a ZrZnON middle layer and lanthanum oxide layers provides higher trap density, allowing for thinner layers, improved capacitive coupling, and enhanced program and erase speeds, while also enabling reduction in operating voltages and better scaling in 3D NAND and CMOS architectures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon nitride is used for charge storage, then the memory cell can store charge, but the trap density is limited and data retention deteriorates, especially with thinner layers
Solution Approach 1:
The patent employs a composite charge storage region comprising multiple layers: a first charge storage layer (silicon nitride), a second charge storage layer (high-k dielectric material such as hafnium oxide, zirconium oxide, or their oxynitrides), and optionally a third charge storage layer. This composite structure combines the advantages of silicon nitride (proven reliability, appropriate band offsets) with high-k dielectrics (higher trap density, better data retention), thereby resolving the contradiction between limited trap density and poor data retention of conventional silicon nitride alone.
Solution Approach 2:
The patent changes the dielectric constant parameter by introducing high-k dielectric materials (k > 7.9) into the charge storage region. This parameter change enables higher trap density and improved data retention without requiring thicker layers, thus resolving the contradiction between trap density and data retention while maintaining thin layer benefits for capacitive coupling.
2Productivity
If the charge storage layer is made thinner to improve capacitive coupling, then cell efficiency improves, but data retention worsens due to reduced trap density
Solution Approach 1:
The composite charge storage region with high-k dielectric layers enables achieving high trap density in thinner layers. The high-k material's superior charge trapping capability compensates for the reduced thickness, maintaining data retention while improving capacitive coupling and cell efficiency. This resolves the contradiction between thin layer benefits and data retention requirements.
Solution Approach 2:
By changing the dielectric constant parameter to high-k values, the patent achieves higher charge storage capacity in thinner layers. The increased k-value compensates for reduced thickness, maintaining adequate trap density and data retention while enabling thinner layers for improved capacitive coupling and cell efficiency.
3Device complexity
If conventional charge storage structures are used, then the device structure is simple, but scaling to 3D NAND and CMOS architectures becomes difficult
Solution Approach 1:
The composite charge storage region with multiple layers (first charge storage layer, second charge storage layer with high-k dielectric, and optionally third charge storage layer) provides a scalable architecture that can be integrated into 3D NAND and CMOS structures. The modular layered design maintains relative structural simplicity while enabling advanced scaling through the superior electrical properties of high-k materials, resolving the contradiction between simplicity and scaling capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The high-k dielectric layers increase charge storage capacity, improve memory cell current, and enhance data retention, allowing for smaller reductions in operating voltages while maintaining performance, thus addressing the limitations of silicon nitride-based cells.
Implementation Method 1
The charge storage region comprises a first charge storage layer, a second charge storage layer comprising a high-k dielectric material, and a third charge storage layer. The high-k dielectric layers increase charge storage capacity
Implementation Method 2
The memory cell is programmed by injecting electrons from the memory cell channel into the charge trapping region
Implementation Method 3
The cell may be erased by injecting holes from the channel into the charge trapping region where they recombine with electrons, and thereby 'cancel' or reduce the stored charge
Data Source
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AI summary
A non-volatile storage device with memory cells having a high-k charge storage region, as well as methods of fabrication, is disclosed. The charge storage region has three or more layers of dielectric materials. At least one layer is a high-k material. The high-k layer(s) has a higher trap density as compared to S13N4. High-k dielectrics in the charge storage region enhance capacitive coupling with the memory cell channel, which can improve memory cell current, program speed, and erase speed. The charge storage region has a high-low-high conduction band offset, which may improve data retention. The charge storage region has a low-high-low valence band offset, which may improve erase.