High-K Dielectric Gate Stack for DRAM Scaling
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Solution Overview
Problem
Conventional silicon-based dynamic memory cells face challenges in scaling down due to the short channel effect, leading to increased transistor area and leakage issues as lithography dimensions shrink below 130 nm, as they require a minimum gate oxide thickness to maintain retention time, which hinders the reduction of channel length and width.
Innovation Solution
The use of a high-K dielectric gate stack with a metal gate electrode in dynamic random access memory cells, which reduces gate leakage and sub-threshold leakage while maintaining equivalent electrical thickness, allowing for scaling down of transistor channel length and width without increasing doping concentration, thereby improving retention time and memory performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If conventional silicon-based dynamic memory cells use a minimum gate oxide thickness of 20 Å or above to maintain retention time, then retention time is improved, but channel length and width cannot be reduced, resulting in larger transistor area
Solution Approach 1:
The patent changes the dielectric constant parameter of the gate oxide material from conventional silicon dioxide (K≈3.9) to high-K dielectric materials (K>20), enabling thinner physical gate oxide while maintaining or improving retention time characteristics
Solution Approach 2:
The patent employs composite gate stack structures combining metal gate electrodes with high-K dielectric materials, creating a multi-material system that achieves both thin physical thickness for scaling and high dielectric constant for charge retention
2Duration of action of stationary object
If conventional silicon-based dynamic memory cells use a minimum gate oxide thickness of 20 Å or above to maintain retention time, then retention time is improved, but transistor area increases
Solution Approach 1:
The patent changes the dielectric constant parameter of the gate oxide material from conventional silicon dioxide (K≈3.9) to high-K dielectric materials (K>20), enabling thinner physical gate oxide while maintaining or improving retention time characteristics
Solution Approach 2:
The patent employs composite gate stack structures combining metal gate electrodes with high-K dielectric materials, creating a multi-material system that achieves both thin physical thickness for scaling and high dielectric constant for charge retention
3Length of moving object
If conventional silicon-based dynamic memory cells scale down lithography dimensions below 130 nm with thinned gate oxide, then transistor size is reduced, but gate leakage increases due to reduced gate oxide thickness
Solution Approach 1:
The patent changes the dielectric constant parameter from conventional silicon dioxide (K≈3.9) to high-K dielectric materials (K>20), allowing the physical gate oxide thickness to be reduced while maintaining adequate electrical thickness to suppress gate leakage currents
Solution Approach 2:
The patent employs composite gate stack structures combining metal gate electrodes with high-K dielectric materials, creating a multi-material system that achieves both thin physical thickness for scaling and high dielectric constant for charge retention
4Speed
If conventional silicon-based dynamic memory cells use thinned gate oxide below 20 Å to maintain channel length to gate oxide thickness ratio, then short channel effect control is improved, but retention time deteriorates due to increased gate leakage
Solution Approach 1:
The patent changes the dielectric constant parameter from conventional silicon dioxide (K≈3.9) to high-K dielectric materials (K>20), allowing the physical gate oxide thickness to be reduced while maintaining adequate electrical thickness to suppress gate leakage currents
Solution Approach 2:
The patent employs composite gate stack structures combining metal gate electrodes with high-K dielectric materials, creating a multi-material system that achieves both thin physical thickness for scaling and high dielectric constant for charge retention
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables the scaling of dynamic memory cells to shorter channel lengths, such as 65 nm and beyond, with improved retention time, reduced leakage currents, and increased drive current, while maintaining or reducing the equivalent electrical thickness of the gate stack.
Implementation Method 1
a gate stack that comprises a high-K dielectric, wherein the high-K dielectric has a dielectric constant greater than the dielectric constant of silicon dioxide
Implementation Method 2
Each of the one or more dynamic random access memory cells comprises a capacitive storage device; and a write access transistor, wherein the write access transistor is operatively coupled to the capacitive storage device
Data Source
AI summary
A dynamic random access memory cell is disclosed that comprises a capacitive storage device and a write access transistor. The write access transistor is operatively coupled to the capacitive storage device and has a gate stack that comprises a high-K dielectric, wherein the high-K dielectric has a dielectric constant greater than a dielectric constant of silicon dioxide. Also disclosed are a memory array using the cells, a computing apparatus using the memory array, a method of storing data, and a method of manufacturing.