High-k Gate Stack Reliability via High Temperature Annealing
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Solution Overview
Problem
The high-k last, metal gate-last process in semiconductor fabrication lacks a built-in high temperature treatment, which affects the reliability of high-k gate stacks, and requires robust encapsulation and challenging etching processes during gate patterning.
Innovation Solution
A method involving the deposition of a high-k dielectric layer followed by a thin metal layer, a sacrificial silicon layer, and a high temperature anneal, with optional additional annealing steps, to enhance the reliability of the gate stack without the need for robust encapsulation and etching during gate patterning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-k last, metal gate-last process is used, then device scaling and power savings are achieved, but reliability of high-k gate stacks deteriorates due to lack of built-in high temperature treatment
Solution Approach 1:
The patent applies preliminary action by forming the high-k dielectric layer before metal gate deposition, allowing it to undergo high temperature annealing treatment that improves reliability. The high-k layer is prepared in advance (high-k first) so it can receive the beneficial thermal treatment before the metal gate is added, resolving the reliability issue without requiring complex post-processing
Solution Approach 2:
The patent segments the gate formation process into two distinct stages: first forming the high-k dielectric layer and annealing it separately, then adding the metal gate layer. This segmentation allows the high-k layer to receive optimized thermal treatment independently, improving reliability while keeping the overall process manageable through clear separation of functions
2Reliability
If gate-first process is used to apply high thermal budget on high-k metal, then reliability improves, but device complexity increases due to robust encapsulation and challenging etching requirements
Solution Approach 1:
The patent inverts the conventional gate-first approach by using high-k first, metal gate-last sequencing. Instead of forming metal gate first and then adding high-k (which requires encapsulation and complex etching), it forms high-k first, anneals it, then adds metal gate. This inversion eliminates the need for robust encapsulation and challenging etching processes while maintaining reliability benefits
Solution Approach 2:
The patent changes the temporal parameter of when high temperature annealing is applied - instead of annealing after metal gate formation (gate-first), it anneals the high-k layer before metal deposition. This parameter change in process sequencing allows high thermal budget treatment without requiring complex encapsulation or etching steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the reliability of high-k gate stacks by allowing a high thermal budget treatment, simplifying the gate formation process, and enhancing device reliability through improved annealing processes, including PBTI, NBTI, and TDDB performance.
Implementation Method 1
annealing the structure at a high temperature of not less than 800° C.
Implementation Method 2
RTA—rapid thermal anneal
Data Source
AI summary
A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.