High κ Gate Stack on III-V Semiconductors
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Solution Overview
Problem
The challenge is to form a high k dielectric stack on a III-V compound semiconductor material with electrical properties sufficient for high-performance FET applications, where the interface between the high k dielectric and the semiconductor material has a low interface state density, as existing solutions face issues with native oxides and complex processing requirements.
Innovation Solution
A method involving surface cleaning to remove native oxides, forming a semiconducting layer in-situ, and depositing a high k dielectric material on a passivated surface, with optional nitridation or oxynitridation to create a stable AOxNy layer, which allows for a high k dielectric with a dielectric constant greater than silicon dioxide, ensuring a low interface state density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If a high k dielectric material is deposited on an unpassivated GaAs surface, then the dielectric constant is increased, but the interface state density becomes high
Solution Approach 1:
A thin semiconducting layer (such as Si, Ge, or their alloys) is formed in-situ on the GaAs surface before depositing the high k dielectric material. This preliminary layer passivates the GaAs surface, preventing the formation of high interface state density when the high k dielectric is subsequently deposited, thus resolving the contradiction between achieving high dielectric constant and maintaining low interface state density.
2Reliability
If Ga2O3 is used as a dielectric on GaAs, then interface state density is reduced, but leakage current increases due to low bandgap
Solution Approach 1:
The patent employs a composite structure consisting of a thin semiconducting layer (Si, Ge, or alloys) combined with a high k dielectric material (such as HfO2, Ta2O5, or other metal oxides with dielectric constant greater than 4.0). This composite structure achieves both low interface state density at the GaAs interface and sufficiently high bandgap to minimize leakage current, overcoming the limitations of using Ga2O3 alone.
3Reliability
If a dual chamber MBE system is used to deposit Ga2O3/Gd2O5 oxide, then interface state density is reduced, but device complexity and manufacturing suitability decrease
Solution Approach 1:
The patent employs a single reactor chamber that can perform multiple functions: forming the thin semiconducting layer, depositing the high k dielectric material, and performing optional nitridation or oxynitridation treatments. This multi-functional approach achieves low interface state density without requiring a complex dual chamber MBE system, thus reducing device complexity while maintaining manufacturing suitability.
4Reliability
If the semiconducting layer is made thinner to reduce capacitance, then interface control is improved, but manufacturing precision becomes more difficult to control
Solution Approach 1:
The patent specifies that the thin semiconducting layer should have a thickness in the range of 0.5 to 5 nm, with a preferred range of 1 to 3 nm. This parameter optimization balances the need for good interface control (achieved by making the layer thin) with manufacturing precision (maintained by not making the layer excessively thin). The in-situ formation process further ensures precise thickness control within this optimized range.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a semiconductor structure with a low interface state density, enabling high-performance FET applications by providing a robust and stable interface, and allowing for precise control of the semiconducting layer thickness and nitride formation without degrading electrical characteristics.
Implementation Method 1
a semiconducting layer which passivates a surface of the III-V compound semiconductor material
Implementation Method 2
a dielectric material having a dielectric constant greater than that of silicon dioxide
Implementation Method 3
converting at least an upper surface region of the semiconducting layer to a region comprised of AOxNy wherein A is a semiconducting material
Data Source
AI summary
A method of forming a high k gate stack on a surface of a III-V compound semiconductor, such GaAs, is provided. The method includes subjecting a III-V compound semiconductor material to a precleaning process which removes native oxides from a surface of the III-V compound semiconductor material; forming a semiconductor, e.g., amorphous Si, layer in-situ on the cleaned surface of the III-V compound semiconductor material; and forming a dielectric material having a dielectric constant that is greater than silicon dioxide on the semiconducting layer. In some embodiments, the semiconducting layer is partially or completely converted into a layer including at least a surface layer that is comprised of AOxNy prior to forming the dielectric material. In accordance with the present invention, A is a semiconducting material, preferably Si, x is 0 to 1, y is 0 to 1 and x and y are both not zero.