Triple-Layer High-k Gate Stack for CMOS Threshold Voltage Tuning
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Solution Overview
Problem
The challenge in the integrated circuit (IC) industry is to provide CMOS devices with proper threshold voltages for both NMOS and PMOS transistors while reducing power consumption, which becomes increasingly difficult as devices scale down to multi-gate structures like FinFET and gate-all-around devices, due to limited room for tuning their threshold voltages using different work function metals.
Innovation Solution
A triple layer high-k gate dielectric stack is used to tune the threshold voltages for both NMOSFET and PMOSFET, employing a common thin layer of work function metal and dipole materials in the lower layers of the stack to adjust the threshold voltage without affecting the work function metal layer, allowing for reliable operation in small devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device dimensions are reduced to multi-gate structures, then production efficiency and cost are improved, but threshold voltage tuning capability deteriorates
Solution Approach 1:
The gate dielectric is segmented into multiple layers with different functions: a first gate dielectric layer adjacent to the channel layer, a second gate dielectric layer over the first layer, and a third gate dielectric layer over the second layer. This segmentation allows each layer to contribute differently to the overall gate work function, enabling fine-grained threshold voltage tuning in scaled devices where traditional single-layer approaches fail.
2Reliability
If work function metals are used for threshold voltage tuning, then device performance is improved, but device complexity increases due to limited room for tuning
Solution Approach 1:
The invention changes the approach from varying metal composition to varying dielectric layer thicknesses and materials. By adjusting the thickness and material composition of the three gate dielectric layers, the effective gate work function can be tuned continuously without introducing multiple different metal layers, thus maintaining device performance while reducing structural complexity.
3Use of energy by moving object
If threshold voltage tuning is performed in small devices, then power consumption is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The invention moves the tuning mechanism from the lateral dimension (metal composition ratios) to the vertical dimension (layer thicknesses). By controlling the thickness of each dielectric layer in the vertical stack, precise threshold voltage tuning is achieved without requiring complex lateral patterning or multiple metal deposition steps, thereby reducing manufacturing precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables flexible tuning of threshold voltages, reducing power consumption and boosting device performance, while maintaining the integrity and reliability of both NMOSFET and PMOSFET in very small sized devices, including FinFET and GAA devices.
Implementation Method 1
employing a common thin layer of work function metal and dipole materials in the lower layers of the stack to adjust the threshold voltage without affecting the work function metal layer
Data Source
AI summary
A method includes providing first and second channel layers in NMOS and PMOS regions respectively of a substrate; depositing a first layer comprising hafnium oxide over the first and second channel layers; forming a first dipole pattern over the second channel layer and not over the first channel layer; driving a first metal from the first dipole pattern into the first layer by annealing; removing the first dipole pattern; depositing a second layer comprising hafnium oxide over the first layer and over the first and second channel layers; forming a second dipole pattern over the second layer and the first channel layer and not over the second channel layer; driving a second metal from the second dipole pattern into the second layer by annealing; removing the second dipole pattern; and depositing a third layer comprising hafnium oxide over the second layer and over the first and the second channel layers.