High-K Gate Structures for Multi-Threshold Voltage FETs
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Solution Overview
Problem
The challenge of manufacturing semiconductor devices with multiple threshold voltages, particularly low and ultra-low threshold voltages, is constrained by the limitations of work function metal layer thicknesses and the complexity of scaling down fin field effect transistors (finFETs) and gate-all-around (GAA) FETs, which complicates the manufacturing process and increases costs.
Innovation Solution
The formation of NFETs and PFETs with different gate structures on the same substrate, utilizing high-K gate dielectric layers doped with metal dopants of varying types and concentrations to induce dipoles of different polarities and concentrations, allowing for the adjustment of effective work function values without altering the work function metal layer thickness, thereby achieving varying threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If work function metal layer thickness is reduced to achieve lower threshold voltages, then threshold voltage control is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent changes the material composition parameter of the high-K gate dielectric layer by introducing metal dopants (such as Al, Ga, In, La, Y, Ce, Eu, Er, Yb, or a combination thereof) at controlled concentrations (1 at% to 20 at%). This parameter change enables threshold voltage adjustment without modifying the work function metal layer thickness, thereby resolving the contradiction between threshold voltage control precision and manufacturing complexity
Solution Approach 2:
The patent creates a composite high-K gate dielectric layer combining HfO2 base material with rare-earth metal or alkaline metal dopants. This composite structure provides multiple threshold voltage levels (e.g., Vt1, Vt2, Vt3 corresponding to 0.8V-1.2V, 0.4V-0.8V, and 0.2V-0.4V respectively) while maintaining a simplified single-layer architecture that reduces manufacturing complexity compared to multi-layer approaches
2Productivity
If finFET and GAA FET dimensions are scaled down to increase storage capacity and processing speed, then device performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent adjusts the metal dopant concentration parameter in the high-K gate dielectric layer to achieve different threshold voltages without changing the physical dimensions of finFET or GAA FET. This allows performance optimization (higher processing speed) while maintaining constant device geometry, thereby avoiding the manufacturing complexity that would otherwise result from further dimension scaling
3Adaptability or versatility
If multiple threshold voltages are implemented to meet diverse device requirements, then adaptability is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent applies local quality by varying the metal dopant concentration at different locations within the high-K gate dielectric layer. Specifically, it creates regions with different dopant concentrations (e.g., 1-10 at% for first threshold voltage, 10-20 at% for second threshold voltage) to generate multiple threshold voltages (Vt1, Vt2, Vt3) in a single layer structure, enabling adaptability without requiring separate manufacturing processes for each threshold voltage level
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the cost-effective and time-efficient production of FETs with smaller dimensions and diverse threshold voltages, reducing manufacturing costs by 20-30% and time by 15-20%, while maintaining reliability and precision.
Implementation Method 1
utilizing high-K gate dielectric layers doped with metal dopants of varying types and concentrations to induce dipoles of different polarities and concentrations, allowing for the adjustment of effective work function values
Data Source
AI summary
A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The semiconductor device includes a first gate structure and a second gate structure. The first gate structure includes a first interfacial oxide (IO) layer, a first high-K (HK) dielectric layer disposed on the first interfacial oxide layer, and a first dipole layer disposed at an interface between the first IL layer and the first HK dielectric layer. The HK dielectric layer includes a rare-earth metal dopant or an alkali metal dopant. The second gate structure includes a second IL layer, a second HK dielectric layer disposed on the second IL layer, and a second dipole layer disposed at an interface between the second IL layer and the second HK dielectric layer. The second HK dielectric layer includes a transition metal dopant and the rare-earth metal dopant or the alkali metal dopant.