High-k Metal Gate CMOS Segmented Work Function Control
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Solution Overview
Problem
Conventional methods for manufacturing semiconductor devices, such as SRAM, face challenges in controlling work function and voltage threshold due to metal residue and intermixing between PFET and NFET work function metals, especially in narrow trenches, which reduces the process window and scalability of barrier metal.
Innovation Solution
A method involving a 'double U' process forms separate high-k dielectric and cap layers around PMOS and NMOS metal gate structures within an Inter Layer Dielectric (ILD) trench, preventing work function metal intermixing and allowing precise control over work functions by forming metal gates in separate processes, with high-k dielectric layers annealed before metal gate formation to reduce defects and thermal exposure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional metal gate deposition is performed in N/PFET poly trenches with photo patterning, then metal gates are formed, but PFET metal residue remains especially in narrow trenches
Solution Approach 1:
The patent segments the metal gate formation process by performing separate metal deposits for NFET and PFET gates at different stages. The first metal deposit forms PFET work function metal in both NFET and PFET trenches, then photo patterning removes PFET metal from NFET trenches. A second metal deposit forms NFET work function metal only in NFET trenches. This segmentation prevents metal residue mixing and improves control over each metal layer.
2Ease of manufacture
If PFET and NFET work function metals are deposited in the same trench, then both gates are formed, but metal intermixing occurs making it difficult to control work function and voltage threshold
Solution Approach 1:
The patent divides the metal deposition into two separate processes: first depositing PFET work function metal (e.g., tungsten) in both NFET and PFET trenches, then removing it from NFET trenches via photo patterning, and second depositing NFET work function metal (e.g., titanium nitride) only in NFET trenches. This ensures each metal layer is formed independently without intermixing, allowing precise control of work functions and threshold voltages for both NFET and PFET devices.
3Manufacturing precision
If a double metal layer is used for NFET gate, then work function control is improved, but the opening in trench becomes quite narrow decreasing process window for metal fill
Solution Approach 1:
The patent implements the double metal layer for NFET gate in a segmented manner: first forming PFET work function metal in both trenches, removing it from NFET trenches, then forming NFET work function metal in the opened NFET trenches. This segmentation allows each metal layer to be deposited and processed in wider openings, maintaining a larger process window for metal fill while still achieving the benefits of a double metal layer structure for precise work function control.
4Manufacturing precision
If the trench opening is narrowed for precise metal layer formation, then work function control improves, but scalability of barrier metal is reduced
Solution Approach 1:
The patent segments the metal gate formation to allow barrier metal scaling. By first forming PFET work function metal in both trenches and removing it from NFET trenches before forming NFET work function metal, the process creates adequate space in NFET trenches for scaling the barrier metal thickness without compromising work function control. This segmented approach enables independent optimization of barrier metal dimensions while maintaining precise work function tuning capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances control over work functions, reduces metal intermixing, and increases the process window for metal fill, enabling more precise tuning of threshold voltage and scalability of barrier metal, thus improving the performance and reliability of semiconductor devices.
Implementation Method 1
performing a second high-temperature annealing to reduce defects in the first high-k dielectric layer
Data Source
AI summary
A semiconductor device includes a dielectric layer on a substrate, a P-type transistor having a first gate stack embedded in the dielectric layer, and an N-type transistor having a second gate stack embedded in the dielectric layer. The first gate stack includes a first metal gate electrode, a first gate dielectric layer underlying the first metal gate electrode, and a first cap layer between the first gate dielectric layer and the first metal gate electrode. The second gate stack includes a second metal gate electrode, a second gate dielectric layer underlying the second metal gate electrode, and a second cap layer between the second gate dielectric layer and the second metal gate electrode. The first and second gate stacks are adjacent, and the first and second metal gate electrodes are separated from each other by the first and second cap layers.