High-k Stacked Capacitor Backend Integration
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Solution Overview
Problem
The continuous shrinkage of microelectronic devices has led to performance limits in traditional materials, particularly silicon dioxide as a dielectric material, which fails to effectively insulate at thin layers, necessitating the use of high-k dielectric materials with high permittivity and stability for capacitors in integrated circuits to enhance device performance and density.
Innovation Solution
A method of forming high-k stacked capacitors by creating holes within a protective overcoat or backend dielectric layer and depositing multiple layers of metal and dielectric materials, with each metal layer electrically tied to an electrode, and alternately depositing dielectric layers between metal layers, ensuring electrical coupling to a contact node in the top metal layer of the integrated circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If silicon dioxide is used as dielectric material and thinned to extend device scaling, then device density is improved, but insulation performance deteriorates due to tunneling current
Solution Approach 1:
The patent changes the dielectric constant parameter by transitioning from silicon dioxide (k≈3.9) to high-k materials such as hafnium oxide (k≥20). This parameter change allows achieving the same capacitance with thicker dielectric layers, thereby maintaining insulation performance while supporting device density scaling.
Solution Approach 2:
The patent employs composite material structures combining high-k dielectric materials with metal electrodes and interface layers. This composite approach optimizes both the insulating properties and the electrical characteristics, resolving the contradiction between maintaining insulation and achieving high device density.
2Ease of manufacture
If traditional silicon and silicon dioxide materials are used, then manufacturing process is simple, but device performance is limited at thin layers
Solution Approach 1:
The patent modifies material parameters by introducing high-k dielectric materials with different physical and chemical properties compared to traditional silicon dioxide. This enables achieving superior device performance at scaled dimensions while managing the increased manufacturing complexity through established deposition techniques.
Solution Approach 2:
The patent introduces interface layers and transition structures as intermediaries between the high-k dielectric materials and the existing silicon-based device architecture. These intermediaries facilitate integration while maintaining compatibility with conventional manufacturing processes, thereby bridging the gap between new materials and existing fabrication capabilities.
3Productivity
If high-k dielectric materials are used to maintain insulation, then device density can be increased, but material stability and interface quality become critical challenges
Solution Approach 1:
The patent employs composite material structures that combine high-k dielectric materials with stable metal electrodes and interface layers. This composite approach enhances overall material stability while maintaining the high dielectric constant necessary for increased device density.
Solution Approach 2:
The patent introduces interface layers as intermediaries between the high-k dielectric materials and the silicon substrate or metal electrodes. These interface layers improve interfacial quality, reduce defects, and enhance the stability of the overall capacitor structure, thereby enabling reliable high-density device operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of high-k stacked capacitors with improved performance characteristics, such as increased device density and effective insulation, addressing the limitations of traditional materials and enhancing the functionality of capacitors in integrated circuits.
Implementation Method 1
new high-k dielectric materials, the need to increase device density, such as capacitors
Implementation Method 2
barrier height to prevent tunneling
Data Source
AI summary
In a disclosed embodiment, a stacked capacitor (100) has bottom, middle and top metal electrode layers (141A, 141B, 141C) interleaved with dielectric layers (142A, 142B) conformally disposed within holes (140A, 140B, 140C) in a protective overcoat or backend dielectric layer (110) over a top metal layer (115) of an integrated circuit (105). A top electrode (155) contacts the top metal electrode layer (141C). A bottom electrode (150) electrically couples an isolated part of the top metal electrode layer (141C) through a bottom electrode via (165A) to a first contact node (135A) in the top metal layer (115) which is in contact with the bottom metal electrode layer (141A). A middle electrode (160) electrically couples a part of the middle metal electrode layer (141B) not covered by the top metal layer (115) through a middle electrode via (165B) to a second contact node (135B) in the top metal electrode layer (115). The sidewalls of the top and middle electrode vias (165A, 165B) are lined with insulating material to electrically isolate the metal electrode layer ends.