High-Q Resonator Lock Control Using TDC Phase Shift Detection

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

High-Q systems in feedback loops face synchronization issues due to frequency changes caused by operational conditions, particularly temperature variations, leading to desynchronization and prolonged lock acquisition times.

Innovation Solution

Implementing a lock range control mechanism with a temperature-dependent limiter and integrator circuit to maintain resonant frequency stability, using a time-to-digital converter loop and delay locked loop to adjust signal frequency based on operational parameters.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a feedback loop is used for high-precision timing circuits, then synchronization of high-Q systems can be achieved, but changes in operational conditions cause frequency changes that result in desynchronization

Engineering Contradiction:
Improvesynchronization stabilityVSAvoidfrequency stability under operational changes
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent applies parameter changes by dynamically adjusting the feedback signal characteristics based on detected phase shifts. The system monitors operational conditions and modifies feedback parameters to compensate for frequency changes, maintaining synchronization stability despite temperature or load variations.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent implements a feedback mechanism where the phase shift of the resonator is continuously detected and used to adjust the feedback loop parameters. This closed-loop control ensures that synchronization is maintained by automatically correcting frequency deviations caused by operational condition changes.

Inventive Principle:
Principle #23Feedback

2Measurement precision

If conventional phase detection circuitry is used, then basic frequency monitoring is achieved, but lock acquisition time is prolonged due to inability to rapidly detect phase shifts

Engineering Contradiction:
Improvephase shift detection accuracyVSAvoidlock acquisition time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent replaces conventional mechanical or analog phase detection circuitry with a digital implementation using a time-to-digital converter. This substitution enables rapid and precise phase shift detection by converting time interval measurements into digital values, significantly reducing lock acquisition time while maintaining high measurement precision.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The system performs preliminary calibration and initialization of the phase detection circuitry before actual operation. By pre-configuring the detection parameters and ensuring the system is ready to immediately track phase shifts, the lock acquisition time is reduced without compromising detection accuracy.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250274128A1Mixed signal electronics for locking control of high-q feedback loops and associated circuitry for detecting phase shift of a resonator
Publication Date: 2025.08.28 PANASONIC OF NORTH AMERICA
  • US20250274128A1 patent drawing
  • US20250274128A1 patent drawing
  • US20250274128A1 patent drawing

AI summary

Circuits for controlling the output of a frequency resonator, specifically for adjusting the output based upon changes in operational parameters such as changes in temperature, are provided. For example, a circuit can include a time-to-digital convertor (TDC) loop configured to be locked to a reference signal and a lock range control (LRC) circuit operably coupled to the TDC loop, the LRC circuit including a sensor and a limiter. The limiter is configured to provide LRC input signal to divider circuitry such that an output of the TDC loop stays close to a resonant value of the reference signal. An alternate circuit can include an integrator circuit path to generate an output signal having an output frequency and a delay loop configured to adjust a reference signal frequency, the delay loop including a delay element configured to offset a phase of the reference signal based upon an initial calibration.