High Resistivity Wafer for 5G RF Parasitic Coupling
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Solution Overview
Problem
Traditional semiconductor-on-insulator (SOI) substrates have resistivity that is not high enough to effectively support the demands of 5G cellular mobile communication RF devices, leading to parasitic coupling issues.
Innovation Solution
A semiconductor structure with a high resistivity wafer is developed, using an insulating material like glass or quartz, which is bonded to a device wafer with an interlayer dielectric layer and a conductive pad, providing a resistivity greater than 10^9 Ohm meters, and a method involving dielectric and conductive layer formation and bonding processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional silicon-on-insulator (SOI) substrate is used, then standard IC technology can be applied, but the resistivity is not high enough for 5G RF devices
Solution Approach 1:
The patent uses a composite structure combining a silicon device layer with a high-resistivity silicon substrate (greater than 10^9 ohm-cm). This composite approach maintains compatibility with standard silicon processing while achieving the high resistivity needed for 5G RF applications, thereby resolving the contradiction between reliability and ease of manufacture.
2Object-affected harmful factors
If high resistivity wafer is used, then parasitic coupling is reduced, but fabrication process becomes more complex
Solution Approach 1:
The patent changes the resistivity parameter of the substrate to greater than 10^9 ohm-cm, which fundamentally reduces parasitic coupling effects in RF devices. By adjusting this material parameter rather than changing the overall device architecture, the fabrication process remains relatively simple while achieving the desired reduction in harmful parasitic coupling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides improved resistivity for RF devices, enhancing their efficiency and reducing parasitic coupling, while using readily available materials and a simpler fabrication process compared to traditional high-resistivity silicon substrates.
Implementation Method 1
a dielectric layer encapsulating the high resistivity wafer, wherein the dielectric layer contacts the interlayer dielectric layer
Implementation Method 2
The bonding process includes bonding the dielectric layer on the second front side to the interlayer dielectric layer
Data Source
AI summary
A semiconductor structure with a high resistivity wafer includes a device wafer. The device wafer includes a front side and a back side. A semiconductor element is disposed on the front side. An interlayer dielectric covers the front side. A high resistivity wafer consists of an insulating material. A dielectric layer encapsulates the high resistivity wafer. The dielectric layer contacts the interlayer dielectric.