High Side Gate Driver Chip Area Reduction
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Solution Overview
Problem
Existing high side gate driver devices face challenges in achieving chip area efficiency as geometry size is scaled down, and traditional fabrication methods are complex, leading to unsatisfactory performance in certain aspects.
Innovation Solution
A method for fabricating a high side gate driver device involving the formation of a drift region, doped extension region, and doped isolation region with specific doping polarities and implantation processes, integrated within a high-voltage junction termination region, which includes a UHV level shifter device to reduce chip area and simplify fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional fabrication methods are used for high side gate driver devices, then manufacturing experience and existing processes can be leveraged, but the fabrication process becomes complicated and chip area efficiency deteriorates as geometry size is scaled down
Solution Approach 1:
The patent combines the level shifter device and the high side gate driver device into a single integrated structure. The level shifter device is formed within the same drift region and shares common components (substrate, drift region, gate structures) with the high side gate driver device, eliminating the need for separate fabrication processes and reducing overall chip area.
Solution Approach 2:
The drift region serves multiple functions: it acts as the drift region for the high side gate driver device, provides the substrate for the level shifter device, and forms part of the junction termination region. This multi-functionality reduces the total chip area required while maintaining all necessary device functions.
2Productivity
If geometry size is scaled down to increase functional density, then more devices can be packed per chip area, but achieving chip area efficiency in existing high side gate driver devices becomes increasingly difficult
Solution Approach 1:
The level shifter device is nested within the drift region of the high side gate driver device. The level shifter's source region, drain region, and gate structure are positioned within and around the drift region, effectively utilizing the same space for multiple device functions and increasing functional density without proportionally increasing chip area.
Solution Approach 2:
The patent utilizes vertical stacking and three-dimensional positioning of regions. The doped extension region extends vertically into the drift region, and the level shifter device is positioned in different vertical planes, effectively using the third dimension to pack more functionality into the same planar footprint.
3Reliability
If a doped extension region with laterally-extending component is formed, then an extra conduction path is provided to reduce on-state resistance, but the device structure becomes more complex
Solution Approach 1:
The doped extension region is formed as part of the same implantation process that creates the level shifter device regions. The extension region shares the same doping polarity and formation process with the level shifter's source and drain regions, integrating the resistance-reduction function into the existing device structure without adding separate processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach reduces chip area, simplifies fabrication processes, and provides an extra conduction path to lower on-state resistance, addressing the inefficiencies of traditional methods while enabling efficient high-voltage operations.
Implementation Method 1
The drift region is implanted to form a doped extension region... The doped extension region has a second doping polarity opposite the first doping polarity
Implementation Method 2
The drift region is implanted to form a doped extension region... at least partially surrounding a portion of the drift region
Data Source
AI summary
The present disclosure provides a semiconductor device. The semiconductor device includes: a drift region having a first doping polarity formed in a substrate; a doped extension region formed in the drift region and having a second doping polarity opposite the first doping polarity, the doped extension region including a laterally-extending component; a dielectric structure formed over the drift region, the dielectric structure being separated from the doped extension region by a portion of the drift region; a gate structure formed over a portion of the dielectric structure and a portion of the doped extension region; and a doped isolation region having the second doping polarity, the doped isolation region at least partially surrounding the drift region and the doped extension region.