High-Voltage Standard Cell Layout for Dense Semiconductor Integration
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Solution Overview
Problem
Existing semiconductor devices face challenges in integrating high-voltage circuits with standard cells due to differences in power supply voltages, leading to increased process complexity and difficulty in forming elements that can withstand higher voltages, particularly with gate-all-around structures.
Innovation Solution
Designing high-voltage circuits as standard cell types, where high-voltage cells are disposed between standard cells without a separate termination region, with heights being an integer multiple of standard cells, and incorporating tolerant elements to manage higher voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high-voltage circuits are implemented with standard cell types and disposed between standard cells without separate termination regions, then integration density is improved and device complexity is reduced, but manufacturing precision becomes more difficult due to voltage differences between adjacent wiring patterns
Solution Approach 1:
A termination region is introduced as an intermediary zone between high-voltage cells and standard cells. This termination region contains wiring patterns that gradually transition in voltage levels, acting as a buffer that reduces the abrupt voltage difference between adjacent high-voltage and low-voltage regions. The termination region thus mediates the voltage transition while allowing the high-voltage circuit to be integrated without separate termination regions, resolving the contradiction between integration density and manufacturing precision.
Solution Approach 2:
The voltage levels of wiring patterns are systematically changed across different regions. In the termination region, wiring patterns have voltage levels that are intermediate between the high-voltage cells and standard cells. This gradual parameter change (voltage level) allows adjacent wiring patterns to have reduced voltage differences, improving manufacturing precision while maintaining high integration density through compact cell arrangement.
2Ease of manufacture
If high-voltage cells are designed with heights that are integer multiples of standard cell heights, then device complexity is reduced and ease of manufacture is improved, but the ability to manage voltage differences becomes more challenging
Solution Approach 1:
The high-voltage cell is segmented into multiple standard cell-height units (integer multiples). Within each segment, wiring patterns are configured to have controlled voltage differences. The segmentation allows the cell to be manufactured using standardized processes while internally managing voltage transitions through carefully designed wiring patterns in each segment, thus maintaining both ease of manufacture and voltage difference control.
Solution Approach 2:
Multiple wiring patterns with different voltage levels are nested within the high-voltage cell structure. The cell contains an hierarchy of wiring patterns where inner patterns have higher voltages and outer patterns have lower voltages, similar to nested dolls. This nesting allows voltage differences to be managed within the standardized cell structure, achieving both ease of manufacture through standardization and precision through controlled voltage gradients.
3Area of stationary object
If wiring patterns in high-voltage cells are disposed on the same height as power lines, then area is reduced and integration density is improved, but voltage differences between adjacent wiring patterns increase
Solution Approach 1:
The physical layout of wiring patterns exhibits asymmetry in voltage distribution. Adjacent wiring patterns are positioned such that their voltage levels are deliberately made similar, creating a symmetric voltage relationship despite potential physical asymmetry in positioning. This asymmetric design allows compact area utilization while maintaining reduced voltage differences between adjacent patterns through careful voltage level assignment rather than uniform spatial distribution.
Data Source
AI summary
A semiconductor device includes a plurality of power lines, a plurality of standard cells having a reference height corresponding to a reference interval between a pair of power lines supplying different power supply voltages, and a high-voltage cell having a height that is an integer multiple of the reference height and disposed between some of the plurality of standard cells. The high-voltage cell includes at least one wiring line disposed at a height of the plurality of power lines in a direction perpendicular to the upper surface of the substrate. The wiring line is disposed at a position equal to a position of a neighboring power line and is physically separated from the neighboring power line.