High-Voltage Schmitt Trigger Using BOXFETs to Avoid SOA Limits
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Solution Overview
Problem
Schmitt triggers in fully depleted semiconductor-on-insulator processing technology platforms face challenges due to low safe operating area (SOA) limitations of laterally diffused metal oxide semiconductor field effect transistors (LDMOSFETs), making them impractical for high voltage input buffers, and require additional circuitry to accommodate high input voltages, increasing complexity and area.
Innovation Solution
A configurable inverting Schmitt trigger design using buried oxide field effect transistors (BOXFETs) with higher voltage rating and LDMOSFETs, connected in series with adjustable reference voltages to prevent SOA violations and tune hysteresis levels, allowing integration into high-voltage receivers without additional circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If LDMOSFETs are used in Schmitt triggers to reduce area consumption, then area is reduced, but safe operating area (SOA) becomes limited making them impractical for high voltage applications
Solution Approach 1:
The Schmitt trigger is divided into two separate circuits: a first Schmitt trigger using LDMOSFETs for area efficiency, and a second Schmitt trigger using high-voltage capable transistors for voltage tolerance. This segmentation allows each circuit to be optimized for its specific function while working together to solve both the area and voltage compatibility problems.
Solution Approach 2:
A voltage translation circuit acts as an intermediary between the low-voltage LDMOSFET-based Schmitt trigger and the high-voltage input signals. This intermediary translates the high-voltage input to a level suitable for the LDMOSFETs, enabling them to operate within their safe operating area while still accepting high-voltage inputs.
2Adaptability or versatility
If additional circuitry is added to accommodate high input voltages, then high voltage capability is achieved, but circuit complexity and area increase
Solution Approach 1:
The patent combines two Schmitt trigger circuits with different voltage capabilities into a single integrated system. The first Schmitt trigger handles area efficiency while the second handles high voltage tolerance, and their combined output provides both high voltage capability and compact area without requiring separate additional protection circuitry.
Solution Approach 2:
The circuit dynamically selects which Schmitt trigger output to use based on the input voltage level. When high voltage inputs are detected, the system activates the high-voltage capable path; when inputs are within normal ranges, it uses the area-optimized LDMOSFET path, thereby adapting to different operating conditions without fixed complexity.
3Area of stationary object
If LDMOSFETs are used for reduced area, then area consumption is reduced, but they cannot tolerate high input voltages up to 5.0V or beyond
Solution Approach 1:
The Schmitt trigger is divided into two separate circuits: a first Schmitt trigger using LDMOSFETs for area reduction, and a second Schmitt trigger using high-voltage capable transistors for voltage tolerance. This segmentation allows each circuit to be optimized for its specific function while working together to solve both the area and voltage compatibility problems.
Solution Approach 2:
The patent creates a composite Schmitt trigger system that combines two different transistor technologies: LDMOSFETs optimized for area efficiency and high-voltage transistors optimized for voltage tolerance. This composite approach leverages the strengths of each transistor type to achieve both compact area and high voltage capability in a single integrated circuit.
Data Source
AI summary
In a disclosed Schmitt trigger, an input stage includes a first p-channel field effect transistor (PFET) and a second PFET, which are connected in series to a VDD rail, and a first n-channel field effect transistor (NFET) and a second NFET, which are connected in series between ground and the second PFET. An output stage includes additional FETs for hysteresis. The first PFET and first NFET are different from the other FETs and have a higher voltage rating. For example, the first PFET and first NFET can be buried oxide field effect transistors (BOXFETs) and the other FETs can be laterally diffused metal oxide semiconductor field effect transistors (LDMOSFETs)). Gates of the first PFET and first NFET are connected to an input node. Gates of the second PFET and NFET are connected to receive reference voltages to prevent safe operating area (SOA) violations and control trigger voltage levels.