Higher Order Multiplexer Architecture Using Enable-Gated Lower MUX
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Solution Overview
Problem
Conventional methods for deriving higher order multiplexers from lower order multiplexers require substantial changes to existing circuitry, leading to increased costs, power consumption, and slowed operations due to the need for additional design, manufacturing, and verification processes.
Innovation Solution
An integrated circuit architecture that allows for the implementation of higher order multiplexers using lower order multiplexers with minimal modification to the baseline circuitry, optimizing circuit design and reducing the need for additional levels of multiplexers, thereby minimizing power consumption and operational slowdowns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional methods are used to derive higher order multiplexers from lower order multiplexers, then the higher order multiplexer functionality is achieved, but the circuit design requires substantial changes leading to increased development costs, manufacturing complexity, and verification time
Solution Approach 1:
The patent makes the existing lower order multiplexer circuitry universal by adding enable signals that allow the same circuit to function as both lower order and higher order multiplexers. The baseline multiplexer design can be configured to operate in different modes (e.g., 32:1 or 64:1) through enable signal control, eliminating the need for separate dedicated circuit designs for each multiplexer order.
Solution Approach 2:
The patent introduces dynamic enable signals that allow the multiplexer circuitry to adapt its functionality at runtime. By dynamically controlling which multiplexer is enabled through enable signals, the system can flexibly switch between different multiplexer configurations without physical reconfiguration, reducing design complexity while maintaining versatility.
2Adaptability or versatility
If conventional methods combine multiple lower order multiplexers to create higher order multiplexers, then the higher order functionality is achieved, but additional levels of multiplexers are required increasing power consumption and operational delay
Solution Approach 1:
The patent extracts the higher order multiplexer functionality from the baseline lower order multiplexer design by selectively enabling specific multiplexers through enable signals. Instead of requiring multiple complete multiplexer levels, the system extracts only the necessary functionality by enabling specific lower order multiplexers based on the higher order select signal, thereby reducing overall power consumption.
Solution Approach 2:
The patent applies partial action by enabling only the specific lower order multiplexers needed for the current higher order selection, rather than having all multiplexers actively operating. This selective enabling reduces the total power consumption while still achieving the higher order multiplexer functionality when needed.
3Adaptability or versatility
If conventional methods combine multiple lower order multiplexers to create higher order multiplexers, then the higher order functionality is achieved, but additional levels of multiplexers increase operational delay and slow down system operation
Solution Approach 1:
The patent extracts the higher order multiplexer capability from the baseline design by using enable signals to selectively activate specific lower order multiplexers. This extraction approach eliminates the need for additional multiplexer levels that would otherwise be required, thereby maintaining fast operation speeds while achieving higher order functionality.
Solution Approach 2:
The patent prepares the higher order multiplexer functionality in advance by having the lower order multiplexer circuitry already present and configured in the baseline design. The enable signals are pre-configured to activate the appropriate multiplexers based on the higher order select signal, eliminating the need for additional signal propagation through extra multiplexer levels and thus maintaining high speed operation.
Data Source
AI summary
Various implementations described herein are directed to an implementation of a higher order multiplexer using lower order multiplexers. In an embodiment, the implementation requires a slight modification to the existing circuitry design of the lower multiplexers. A plurality of multiplexers may be coupled with each other such that a common input port and output port is formed. Using an enable signal, only one of the coupled multiplexers may be enabled at a time while the remaining multiplexers are switched off. Therefore, upon receiving a select signal indicating an address of a memory cell, the lower multiplexers coupled together function as a higher order multiplexer in selecting the appropriate column corresponding to the memory cell.